Direct Chip Shielding Layer for EMI-Safe Package Miniaturization
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the occupation of space by shielding walls, which also constrain wiring and functionality enhancement.
Innovation Solution
A shielding layer is directly formed on the surface of electronic components, covering their inactive and side surfaces, with a redistribution layer electrically connected to the component, reducing the package size and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a shielding wall is provided around semiconductor chips to prevent electromagnetic interference, then electromagnetic shielding is improved, but the package substrate area is occupied and wiring area is reduced
Solution Approach 1:
The patent transitions from a planar shielding wall structure on the substrate surface to a three-dimensional shielding layer formed directly on the vertical surfaces of semiconductor chips. This dimensional change allows shielding functionality to be achieved without occupying substrate area, as the shielding layer is formed on the chip sidewalls and top surface rather than on the substrate plane.
Solution Approach 2:
The shielding layer is integrated directly onto the semiconductor chip structure itself, nesting the shielding function within the chip package rather than as a separate external component. The shielding layer covers the chip body and sidewalls, effectively embedding the shielding functionality into the chip structure to avoid additional space requirements.
2Object-affected harmful factors
If a shielding wall is provided around semiconductor chips to prevent electromagnetic interference, then electromagnetic shielding is improved, but wiring area is reduced and functionality enhancement is constrained
Solution Approach 1:
By moving the shielding structure from the substrate plane to the chip vertical dimension, the patent frees up substrate wiring area while maintaining shielding effectiveness. The shielding layer formed on chip sidewalls and top surfaces does not interfere with substrate routing, allowing enhanced wiring density and functional integration.
3Object-affected harmful factors
If conventional shielding structures are used, then electromagnetic shielding is achieved, but the package size cannot be reduced further
Solution Approach 1:
The shielding layer is nested directly onto the semiconductor chip structure, utilizing the chip's own geometry to provide shielding. This integration eliminates the need for separate shielding components that would increase package size, allowing continued miniaturization while maintaining EMI protection.
Data Source
AI summary
An electronic package and a manufacturing method thereof are provided. The electronic package includes an electronic component and a shielding layer. The electronic component has an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface and the active surface. The shielding layer is disposed on the electronic component and directly contacts and completely covers the inactive surface and the side surface. The shielding layer is formed directly on the surface of the electronic component, thereby shielding electromagnetic interference, reducing the size of the electronic package, and lowering production costs.