Surface-Mount Chip Side Metallization With Porous Silicon Insulation
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Solution Overview
Problem
Existing methods for producing surface-mount chips with metallizations extending through lateral portions on the sides of the chip face practical implementation difficulties and inadequate insulation, which complicates the soldering process, especially in sensitive sectors like automotive and medical industries.
Innovation Solution
A surface-mount chip design featuring a silicon substrate with a front face and sidewall, including a metallization with a first portion on the front face and a second portion on the side, separated by a porous silicon region forming a hollow vertical channel in a groove, ensuring proper insulation and facilitating visual inspection of connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If metallization extends onto the side of the chip to enable visual inspection of soldering, then connection quality inspection is improved, but insulation between metallization and substrate deteriorates
Solution Approach 1:
A porous silicon layer is introduced as an intermediary substance between the metallization and the substrate. This porous silicon layer provides both electrical insulation and mechanical support, allowing the metallization to extend onto the chip side while maintaining proper insulation from the substrate.
Solution Approach 2:
The patent utilizes porous silicon material to create an insulating region. The porous structure provides effective insulation while occupying minimal space, enabling the metallization to extend laterally without compromising insulation quality. The porous nature also allows for better adhesion and integration with surrounding structures.
2Reliability
If metallization is separated from substrate by insulating region, then insulation quality is improved, but manufacturing complexity increases
Solution Approach 1:
The porous silicon layer serves as the insulating region, utilizing the inherent properties of porous silicon to provide effective electrical insulation. This approach maintains structural simplicity while achieving the required insulation quality, as porous silicon can be integrated into existing semiconductor manufacturing processes.
Solution Approach 2:
The patent employs a composite structure combining porous silicon and insulating material to create the insulating region. This composite approach optimizes both insulation performance and manufacturing feasibility, allowing for reliable insulation without excessive structural complexity.
3Ease of manufacture
If existing methods are used to produce surface-mount chip with lateral metallization, then production process is simplified, but practical implementation difficulties arise
Solution Approach 1:
The porous silicon layer acts as a mediator that enables reliable soldering by providing a stable, insulating interface between the metallization and substrate. This intermediary layer ensures proper thermal and electrical properties during the soldering process, resolving implementation difficulties while maintaining manufacturing simplicity.
Solution Approach 2:
The porous silicon structure facilitates reliable soldering by providing adequate thermal conduction during brazing while maintaining electrical insulation. The porous nature allows for better material adherence and connection quality, solving practical implementation issues without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for effective soldering and visual inspection of connections, reduces capacitive couplings and short-circuit risks, and enables easy adaptation of insulation thickness to meet application needs, improving the reliability and quality of chip connections.
Implementation Method 1
a region of porous silicon, included in the substrate, separating the second portion of the metallization from the rest of the substrate
Implementation Method 2
reduces capacitive couplings and short-circuit risks
Implementation Method 3
the metallizations intended to be soldered to an external device extend through lateral portions on the sides of the chip. When brazing is performed, some of the brazing material adheres to the side portions of the metallizations, allowing visual inspection of the quality of the connections
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The invention relates to a surface mount chip produced in and on a silicon substrate having a front face and a sidewall, the chip comprising: at least one metallization intended to be soldered to an external device, this metallization comprising a first portion ( 30a) covering at least part of the front face of the substrate, and a second portion (30b) covering at least part of the side of the substrate; and a porous silicon region (20), included in the substrate, separating the second portion (30b) of the metallization from the rest of the substrate.