Chip Side Wall Passivation via Bosch Polymer Integration

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Solution Overview

Problem

Current methods for manufacturing chip side wall passivation are complex and require additional process steps, particularly after the Bosch process, where the polymer layer deposited during etching is typically removed, leaving a blank silicon surface.

Innovation Solution

The method involves using the polymer layer deposited during the Bosch process, strengthening and thickening it instead of removing it, and subsequently forming additional polymer layers to create a passivation layer for chip side walls without additional process steps, utilizing alternating processes of deposition and etching to achieve the desired thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the polymer layer deposited during the Bosch process is removed to leave a blank silicon surface, then the chip side wall is exposed and ready for subsequent processing, but an additional side wall passivation process step is required

Engineering Contradiction:

Improvechip side wall preparationVSAvoidpassivation process steps

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the side wall passivation function with the polymer layer already deposited during the Bosch etching process. By integrating the passivation layer formation into the existing Bosch process sequence, the method eliminates the need for a separate side wall passivation step, thereby reducing process complexity while maintaining ease of manufacture

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The polymer layer deposited during the Bosch process serves dual purposes: it acts as an etch mask during the etching process and simultaneously provides side wall passivation protection. This multi-functionality eliminates the need for separate passivation processing, resolving the contradiction between ease of manufacture and device complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a separate side wall passivation process is added after the Bosch process, then the chip side walls are protected, but the manufacturing process complexity increases

Engineering Contradiction:

Improvechip side wall protectionVSAvoidmanufacturing process steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the side wall passivation function with the polymer layer already deposited during the Bosch etching process. By integrating the passivation layer formation into the existing Bosch process sequence, the method eliminates the need for a separate side wall passivation step, thereby reducing process complexity while maintaining ease of manufacture

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The polymer layer deposited during the Bosch process automatically serves as the side wall passivation layer. The process utilizes the byproduct of the etching process itself to provide the protective function, eliminating the need for additional dedicated passivation process steps while ensuring reliable side wall protection

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the passivation process by integrating it into the Bosch process, providing a robust passivation layer that protects chip side walls and can be thickened to a desired thickness, reducing complexity and the need for extra steps in chip arrangement and package manufacturing.

Implementation Method 1

forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material

Methodology Applied

Scientific EffectPolymer deposition: Deposition (physical)

Implementation Method 2

selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material

Methodology Applied

Scientific EffectSelective etching:

Data Source

PatentUS9576875B2Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

Publication Date: 2017.02.21 INFINEON TECHNOLOGIES AG

AI summary

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.