Semiconductor Chip Sidewall Sealing via Anodized Dicing Trenches

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Solution Overview

Problem

Semiconductor chip side walls are prone to mechanical and chemical damage during and after separation from the wafer, particularly due to metal plating and soldering processes that compromise chip integrity.

Innovation Solution

Form dicing trenches in a semiconductor wafer and anodize the side walls to generate an anodic oxide layer, using an electrolyte temperature of 70°C or higher, optionally with dopant implantation or illumination, to create a high-quality, conformal, and hermetic seal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional dicing methods are used to separate chips from wafer, then chip separation is achieved, but chip side walls are damaged and integrity is compromised

Engineering Contradiction:
Improvechip separationVSAvoidchip side wall integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Anodic oxide layers are formed on the chip side walls before the dicing separation process. This preliminary protective coating is applied to the wafer while chips are still attached, ensuring that the side walls are sealed and protected before they are exposed to mechanical stress during separation and subsequent handling.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The anodic oxide layer acts as a cushioning protective barrier formed beforehand on the chip side walls. This oxide layer absorbs and distributes mechanical stresses during dicing and handling, preventing direct damage to the underlying semiconductor material and maintaining side wall integrity throughout the manufacturing process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Ease of manufacture

If metal plating and soldering processes are applied after chip separation, then packaging is completed, but chip side walls suffer mechanical and chemical damage

Engineering Contradiction:
Improvepackaging process completionVSAvoidside wall damage from plating and soldering
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The anodic oxide layer serves as an intermediary protective barrier between the chip side walls and the harmful metal plating and soldering processes. This oxide layer is chemically resistant and prevents direct contact between aggressive plating/soldering chemicals and the semiconductor material, eliminating contamination and damage while allowing the packaging processes to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If anodic oxidation is performed at low temperature, then energy consumption is reduced, but the quality and conformality of the anodic oxide layer is insufficient

Engineering Contradiction:
Improveenergy consumption during anodizingVSAvoidanodic oxide layer quality and conformality
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent optimizes the anodizing process by maintaining electrolyte temperature within a specific range (20°C to 100°C, with preferred ranges of 40°C-70°C or 60°C-80°C). This parameter control ensures formation of high-quality, conformal anodic oxide layers with appropriate thickness and structural integrity, balancing energy consumption with manufacturing precision for side wall protection.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The anodic oxide layer effectively protects the chip side walls from damage, ensuring uniformity and integrity during subsequent manufacturing processes, including metal deposition and soldering, by providing a reliable and conformal seal.

Implementation Method 1

The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches

Methodology Applied
Scientific EffectAnodic oxidation: Anodising

Implementation Method 2

wherein a temperature of an electrolyte during anodizing is equal to or higher than 70°C

Methodology Applied
Scientific EffectThermal heating: Heating

Data Source

PatentEP3987565B1Method of manufacturing semiconductor chips having a side wall sealing
Publication Date: 2025.08.20 INFINEON TECH AUSTRIA AG
  • EP3987565B1 patent drawingFigure 1~2
  • EP3987565B1 patent drawingFigure 3(a)~5
  • EP3987565B1 patent drawingFigure 6

AI summary

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.