Chip Singulation via Trench Etching and Passivation
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Solution Overview
Problem
Current wafer dicing methods, such as classical blade dicing and laser cutting, cause significant sidewall damage and require wide scribe lanes, while trench etch dicing is limited by the presence of electrical test structures and alignment features, leaving die edges unprotected and unsingulated.
Innovation Solution
A method involving etching singulating trenches through the back end of line, front end of line, and substrate layer, followed by depositing a passivation layer on the stack with trenches, and then releasing the chip, which can include blade, laser, or trench etch dicing between trenches, allowing for narrower scribe lanes and protected die edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If classical blade dicing is used, then die singulation can be achieved, but significant sidewall damage and wide scribe lanes are required
Solution Approach 1:
The method performs preliminary actions by etching trenches and depositing passivation layers before final singulation. The passivation layer is deposited over the trenches to protect sidewalls before the dicing process, preventing sidewall damage during separation while allowing narrower scribe lanes.
Solution Approach 2:
The passivation layer acts as an intermediary protective layer between the trench walls and the dicing process. This intermediate layer prevents direct contact between the dicing blade/laser and the trench sidewalls, eliminating mechanical or thermal damage while enabling tighter scribe lane spacing.
2Manufacturing precision
If laser cutting is used, then sidewall chipping is eliminated, but heat-affected zones require exclusion areas and wide scribe lanes
Solution Approach 1:
The passivation layer is deposited before laser dicing to provide thermal protection. This preliminary protective layer absorbs and distributes the laser heat, preventing direct thermal exposure to the trench sidewalls and eliminating the need for large heat-affected exclusion zones.
Solution Approach 2:
The passivation layer serves as a thermal intermediary between the laser beam and the trench sidewalls. It absorbs excess heat and prevents direct thermal coupling, protecting the sidewalls from laser-induced damage while allowing narrower scribe lanes without exclusion areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces sidewall damage, allows for narrower scribe lanes, and provides protected die edges, enhancing the reliability of chips, especially those with moisture-sensitive materials, and eliminates the need for space-consuming sealing rings.
Implementation Method 1
etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer of the stack
Implementation Method 2
depositing a passivation layer on the stack provided with singulating trenches, such that sidewalls of the trenches are at least partially passivated
Data Source
AI summary
The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.