Chip Size Package Fabrication Using Pre-Formed Via Holes
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Solution Overview
Problem
Current chip size package fabrication methods are costly due to the use of expensive materials and inefficient processing steps, with a need to maximize yield and minimize errors in semiconductor device assembly.
Innovation Solution
The semiconductor device employs a lamination member with pre-formed via holes to reduce processing operations, incorporates fiducial patterns for accurate die placement, and eliminates the use of costly thermosensitive sheets, allowing for simplified manufacturing and improved yield through reduced photolithography and plating steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional chip size package fabrication methods are used, then manufacturing cost is reduced through material selection, but processing complexity and error rates increase due to multiple photolithography and plating steps
Solution Approach 1:
Via holes are pre-formed in the lamination member before die attachment, eliminating the need for subsequent via hole formation steps. This preliminary action reduces processing complexity and minimizes opportunities for errors while maintaining cost effectiveness through simplified manufacturing
Solution Approach 2:
Multiple functions are merged into the lamination member structure: it serves as both the substrate and contains pre-formed via holes for conductive connections. This consolidation eliminates separate processing steps for via hole formation and reduces the overall number of manufacturing operations required
2Manufacturing precision
If multiple photolithography and plating steps are performed, then conductive patterns are formed with precise dimensions, but manufacturing cost increases and yield decreases
Solution Approach 1:
Via holes are pre-formed with precise dimensions before die attachment, ensuring accurate conductive pattern formation without requiring multiple subsequent photolithography and plating steps. This preliminary precision work reduces rework and improves overall yield
Solution Approach 2:
The complex multi-step photolithography and plating process is extracted and replaced by pre-formed via holes in the lamination member. This extraction eliminates unnecessary processing steps that increase cost and reduce yield while maintaining the required precision through the pre-formed structure
3Device complexity
If fiducial patterns are not used, then manufacturing process is simpler, but die placement accuracy and alignment precision deteriorate
Solution Approach 1:
Fiducial patterns provide visual references that enable precise alignment and measurement during die placement. These patterns create detectable features that improve measurement precision without significantly increasing process complexity
Solution Approach 2:
Manual or mechanical alignment methods are replaced by using fiducial patterns that enable optical or automated alignment systems to achieve higher precision die placement accuracy through pattern recognition and measurement
Data Source
AI summary
A semiconductor device and a fabricating method thereof are provided. In one exemplary embodiment, a plurality of semiconductor dies are mounted on a laminating member, for example, a copper clad lamination, having previously formed conductive patterns, followed by performing operations of encapsulating, forming conductive vias, forming a solder resist and sawing, thereby fabricating a chip size package in a simplified manner. Fiducial patterns are further formed on the laminating member, thereby accurately positioning the semiconductor dies at preset positions of the laminating member.