Chip Socket Assembly for Fine-Pitch Probe-to-Pad Alignment
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Solution Overview
Problem
The miniaturization of electrode pads in semiconductor chips poses challenges in accurately aligning probes of a socket apparatus with the pads, exacerbated by manufacturing tolerances and differing alignment references, leading to connection alignment errors during electrical testing.
Innovation Solution
A chip socket assembly with a chip guide member, bump guide member, and intermediate fastening member, utilizing alignment pins and probes, to precisely guide and align semiconductor chips, enhancing alignment accuracy through coordinated reference points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the electrode pad size and pitch are reduced to achieve higher integration, then the manufacturing capability and device density are improved, but the alignment accuracy between probes and pads deteriorates
Solution Approach 1:
The patent introduces an intermediary alignment mark structure that includes a first alignment mark on the socket apparatus and a second alignment mark on the semiconductor device. These alignment marks serve as mediators to transfer and coordinate the alignment reference between the socket and the device, enabling accurate probe-to-pad alignment even when the electrode pitch is reduced to 65 μm or less.
Solution Approach 2:
The patent adds a new dimensional element to the alignment system by introducing alignment marks that extend beyond the traditional probe-to-pad direct alignment approach. The alignment marks create an additional alignment dimension that decouples the alignment reference from the electrode pitch scale, allowing independent optimization of both device miniaturization and alignment accuracy.
2Adaptability or versatility
If different alignment references are used for socket apparatus and semiconductor device, then the design flexibility is improved, but the alignment accuracy between probes and pads deteriorates
Solution Approach 1:
The patent merges the alignment reference systems of the socket apparatus and semiconductor device by establishing a common alignment mark coordinate system. The first alignment mark on the socket and the second alignment mark on the device are designed to correspond to each other, creating a unified alignment reference that coordinates both components while maintaining their individual design flexibilities.
3Ease of manufacture
If machining tolerances and device size tolerances are accommodated with design margin, then the manufacturing feasibility is improved, but the alignment tolerance for fine pitch electrodes deteriorates
Solution Approach 1:
The alignment marks serve as intermediary reference elements that are less sensitive to machining and device size tolerances than the electrode pads themselves. By using these dedicated alignment marks as the primary reference, the system can accommodate larger manufacturing tolerances in the socket and device while maintaining tight alignment tolerance for the probe-to-pad connection.
Data Source
AI summary
Disclosed are a chip socket assembly for semiconductor chip testing and a semiconductor chip testing apparatus including the same. The chip socket assembly includes a chip guide member having a chip guide hole through which a chip having a plurality of bumps and a plurality of pads formed on one surface thereof is inserted and guided, a bump guide member having at least one bump guide hole configured to guide the positions of at least some of the bumps and at least one pad exposure hole configured to expose at least some of the pads, an intermediate fastening member having an opening configured to expose at least a part of the one surface of the chip on which the bumps and the pads are formed, and a chip socket substrate provided on one surface thereof with a plurality of probes configured to contact at least some of the pads.