Chip Source Grounding Layout for Low Parasitic Inductance
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Solution Overview
Problem
Parasitic inductance in transistor sources due to conductive wire bonding increases, reducing transistor gain and requiring larger chip areas and higher costs when grounded through substrate back holes.
Innovation Solution
A chip preparation method using front-side lithography to form epitaxial layers and source conducting layers in a stacked manner, ensuring full contact and reducing layout areas by using high-precision etching to avoid over-etching and incorrect etching of source conducting layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the source is grounded through conductive wire bonding, then the transistor structure is simple, but parasitic inductance increases and transistor gain is reduced
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical grounding through back holes. The source is grounded by forming conductive paths through the substrate thickness direction, creating a vertical connection that eliminates parasitic inductance while maintaining structural simplicity.
Solution Approach 2:
The patent introduces back holes as intermediary structures to establish the grounding path. These holes filled with conductive material serve as mediators between the source and ground plane, providing a low-inductance connection without requiring external wire bonds.
2Reliability
If the back hole is designed right below the source metal, then parasitic parameters are reduced, but the source metal width increases and chip area increases
Solution Approach 1:
The patent applies local quality by concentrating the grounding function specifically in the regions where back holes are formed beneath the source metal. The source metal pattern is locally optimized to align with the back hole positions, allowing narrow source metal widths while maintaining effective grounding where needed.
Solution Approach 2:
The back holes are formed and filled with conductive material before the source metal is deposited. This preliminary preparation of grounding paths allows the source metal to be deposited in narrow patterns that precisely align with the pre-formed conductive pillars, minimizing chip area while ensuring low parasitic parameters.
3Manufacturing precision
If front-side lithography is used to etch the epitaxial layer, then lithography precision is improved and over-etching is avoided, but the process complexity increases
Solution Approach 1:
Instead of performing etching from the back side of the substrate, the patent inverts the approach by etching the epitaxial layer from the front side. This reversal of the etching direction enables precise lithographic control and alignment, preventing over-etching while maintaining process efficiency.
Data Source
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AI summary
Embodiments of this application provide a chip, a chip preparation method, a radio frequency power amplifier, and a terminal, and relate to the field of semiconductor technologies, to ensure that an epitaxial layer is in full contact with a source conducting layer. The chip includes a first transistor and a second transistor, and the method includes: forming, on a substrate (10), an epitaxial layer (11) and a source conducting layer (21) that are sequentially disposed in a stacked manner, where the epitaxial layer includes a first via, to form a first epitaxial layer (101) of the first transistor and a second epitaxial layer (102) of the second transistor; the source conducting layer includes a first source (211) of the first transistor and a second source (212) of the second transistor; and an edge of the first source (211) is flush with an edge of the first epitaxial layer (101) close to a side of the first via, and an edge of the second source (212) is flush with an edge of the second epitaxial layer (102) close to a side of the first via; forming a first conducting layer (13) in the first via, where the first conducting layer (13) is in contact with the first source (211) and the second source (212); forming a second via; and forming a second conducting layer (14) in the second via, where the second conducting layer (14) is in contact with the first conducting layer (13) and is grounded.