Chip Stack Structure with Selective Adhesive Bonding
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Solution Overview
Problem
Existing three-dimensional chip integration techniques face challenges such as high residual stress from bonding processes, incomplete adhesive removal, and fragile bonding interfaces, which affect processing yields and reliability in high-density chip packages.
Innovation Solution
A chip stack structure comprising a first chip, multiple second chips, an adhesive, and an encapsulant, where the second chips are stacked with penetrating electrodes and bonded to the first chip using a selective adhesive that voids space, and the encapsulant covers the adhesive and side surfaces to fill voided spaces, reducing stress and improving bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high temperature bonding process is used to bond chips, then bonding strength is improved, but residual stress increases
Solution Approach 1:
The patent changes the bonding parameters by using low temperature bonding process instead of high temperature bonding, thereby reducing residual stress while maintaining bonding strength through optimized bonding conditions and material selection
Solution Approach 2:
The patent employs composite material structures including adhesive layers with specific material properties that enable strong bonding at lower temperatures, reducing thermal stress while achieving required bonding strength
2Loss of substance
If adhesive is completely removed after bonding, then cleanliness is improved, but bonding interface strength decreases
Solution Approach 1:
The patent applies preliminary protective actions by coating the bonding interface with specific materials before bonding that prevent adhesive contamination of the bonding interface, eliminating the need for adhesive removal while maintaining bonding strength
Solution Approach 2:
The patent introduces intermediary protective layers or coatings at the bonding interface that act as barriers to adhesive contamination, allowing complete adhesive removal without compromising bonding interface strength
3Quantity of substance
If small scribe line is used in high density chip package, then chip density is improved, but dispensing process difficulty increases
Solution Approach 1:
The patent transitions from planar dispensing to three-dimensional dispensing approaches, allowing adhesive application in high density packages by utilizing vertical or angled dispensing paths that accommodate small scribe lines while maintaining manufacturing ease
Solution Approach 2:
The patent replaces traditional mechanical dispensing systems with alternative methods such as automated dispensing robots or precision-controlled dispensing mechanisms that can accurately place adhesive in confined spaces with small scribe lines
4Ease of operation
If wafer is temporarily attached to carrier via adhesive, then wafer handling is improved, but adhesive removal completeness decreases
Solution Approach 1:
The patent employs disposable or single-use carrier adhesives that are designed to be easily removed without leaving residues, sacrificing carrier reusability to achieve complete adhesive removal and maintain wafer handling effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances processing yields, reduces manufacturing costs, and improves the reliability of high-density chip packages by minimizing stress and eliminating the need for an interposer, while allowing high-temperature bonding and wafer-level processing.
Implementation Method 1
The adhesive is disposed in a space between any two adjacent chips of the first chip and the at least one second chip with voiding a part of the space, wherein the adhesive is configured to cover each of the first bumps and the corresponding first contact or the corresponding second bump
Implementation Method 2
The encapsulant is disposed on the first surface to cover the adhesive and the side surfaces of each of the at least one second chip, wherein the voided space between the any two adjacent chips is filled with the encapsulant
Implementation Method 3
a plurality of first penetrating electrodes connected between the corresponding first bumps and second bumps
Data Source
AI summary
A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided.