Chip Stack Bond Pad Layout for Reliable Backside Connections
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Solution Overview
Problem
Conventional chip stacking techniques face issues with unreliable and complex external connections, prone to short-circuit failures and moisture ingress, which can cause corrosion and reliability failures due to thin bond pads and precise etching requirements.
Innovation Solution
The solution involves placing a bond pad within the top chip, extending beyond the etched opening, with a larger size and thickness to reduce cracking and short-circuit risks, and using a metal seal ring or moisture-resistant dielectric materials to block moisture ingress, facilitating easier etching and enhancing connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bond pad is placed within the top chip extending beyond the etched opening with larger size and thickness, then the risk of cracking and short circuits is reduced, but the device complexity increases
Solution Approach 1:
The bond pad is positioned in a different spatial arrangement - extending beyond the etched opening in the top chip rather than being confined within it. This dimensional change allows the bond pad to be accessible from the backside surface while maintaining its electrical connection function, thereby reducing cracking and short-circuit risks without significantly increasing overall device complexity
Solution Approach 2:
The etched opening acts as an intermediary structure that provides access to the bond pad extending beyond it. This intermediary approach allows the bond pad to be both protected within the chip structure and accessible for external connections, resolving the contradiction between reliability and complexity
2Object-affected harmful factors
If metal seal ring or moisture-resistant dielectric materials are used to block moisture ingress, then moisture protection is improved, but the ease of manufacture decreases
Solution Approach 1:
The patent changes the material parameters by using moisture-resistant dielectric materials with specific properties (low moisture absorption, high barrier performance) to block moisture ingress paths. This parameter change improves moisture protection while the materials selected maintain compatibility with standard semiconductor manufacturing processes
Solution Approach 2:
The patent employs composite material structures combining metal seal rings with moisture-resistant dielectric materials to create a multi-layer barrier system. This composite approach provides superior moisture protection compared to single materials, while the modular nature of composite structures allows for systematic integration into manufacturing processes
3Manufacturing precision
If precise etching is required for conventional bond pad connections, then manufacturing precision must be high, but the ease of manufacture decreases
Solution Approach 1:
The bond pad is pre-positioned to extend beyond the etched opening area before etching is performed. This preliminary action allows the etching process to be less precise, as the bond pad's extended position ensures it will be accessible even with variations in etching depth and dimensions, thereby reducing the stringency of manufacturing precision requirements
Solution Approach 2:
The bond pad has non-uniform geometry with different dimensions in different regions - a larger extended portion beyond the opening and a smaller portion within the chip. This local quality variation allows the exposed portion to be accessible for connections while the covered portion maintains electrical connectivity, reducing overall etching precision requirements
Data Source
AI summary
A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.