Chip Stack Bonding Channels for Lower Parasitic Capacitance
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Solution Overview
Problem
The reduction of interconnection spacing in chip stacked structures increases parasitic capacitance, leading to increased resistive-capacitive delay and reduced signal transmission performance.
Innovation Solution
Incorporating channels with a dielectric constant less than the dielectric constant of the dielectric layer between adjacent bonding devices, reducing parasitic capacitance and thereby minimizing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnection spacing is reduced to increase interconnection density, then bandwidth and power consumption are improved, but parasitic capacitance increases leading to increased RC delay and reduced signal transmission performance
Solution Approach 1:
The patent applies local quality by creating channels with different dielectric constants in specific locations between adjacent bonding devices. Instead of uniformly changing the dielectric layer throughout, the invention selectively modifies the dielectric constant in localized regions where parasitic capacitance is most problematic, thereby reducing RC delay without compromising overall interconnection density
Solution Approach 2:
The patent changes the dielectric constant parameter of the dielectric layer by forming channels filled with materials having different dielectric constants (such as air, vacuum, or low-k materials) compared to the surrounding dielectric layer. This parameter change directly reduces parasitic capacitance between adjacent bonding devices, thereby improving signal transmission performance while maintaining the reduced interconnection spacing
2Power
If interconnection spacing is reduced to continuously increase interconnection density, then bandwidth is improved, but parasitic capacitance between adjacent bonding devices increases
Solution Approach 1:
The invention introduces channels with distinct dielectric properties in specific locations between bonding devices, creating local variations in dielectric quality. These localized channels reduce parasitic capacitance in the most critical areas without requiring a complete redesign of the entire interconnection structure
Solution Approach 2:
The patent converts the harmful effect of closely spaced bonding devices (which generate parasitic capacitance) into a benefit by strategically placing channels with optimized dielectric constants between them. The close spacing that originally caused harm is now managed through the channel structure, allowing high interconnection density to coexist with reduced parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, enhancing signal transmission performance by decreasing the RC delay in the chip.
Implementation Method 1
a channel between the first bonding device and the second bonding device is formed at the first dielectric layer, and a dielectric constant of the channel is less than a dielectric constant of a material of the first dielectric layer
Data Source
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AI summary
Embodiments of this application provide a chip, a chip stacked structure, a chip package structure, and an electronic device, and relate to the field of semiconductor technologies. The chip is bonded with another chip via a dielectric layer and a plurality of bonding devices that penetrate the dielectric layer, and implements signal interworking. Parasitic capacitance generated between two adjacent bonding devices of the chip is small, so that signal transmission performance of the chip is improved. The chip includes: a die; and a first dielectric layer disposed on a side of the die, and a plurality of bonding devices that penetrate the first dielectric layer. The plurality of bonding devices include a first bonding device and a second bonding device that are adjacent to each other, a channel between the first bonding device and the second bonding device is formed at the first dielectric layer, and a dielectric constant of the channel is less than a dielectric constant of a material of the first dielectric layer.