Chip-Stacked Package Capacitance Sensing for Alignment and Gap Detection

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Solution Overview

Problem

The reliability of chip-stacked semiconductor packages depends on the stacking quality, which is challenging to evaluate effectively due to the need for precise measurement of stacking accuracy and joint gaps between chips during the manufacturing process.

Innovation Solution

A chip-stacked semiconductor package design incorporating detection pads and test terminals that measure capacitance between pads to assess stacking accuracy and joint gaps, allowing for non-destructive evaluation during in-line manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional stacking methods are used without detection pads, then the manufacturing process is simpler, but stacking accuracy and joint gap detection are insufficient

Engineering Contradiction:

Improvestacking accuracy detectionVSAvoiddetection pad structure

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces detection pads as intermediary elements between the chips and the measurement system. These pads serve as mediators that enable capacitance measurement to detect stacking accuracy and joint gaps without requiring direct complex measurement equipment on the chips themselves.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces direct mechanical measurement methods with electrical capacitance measurement. Instead of using physical probes or mechanical gauges to measure stacking accuracy, the system uses electrical fields and capacitance changes to detect positional deviations and gaps non-contactly.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If capacitance measurement method is implemented, then stacking quality can be detected accurately, but the manufacturing process becomes more complex

Engineering Contradiction:

Improvechip-stacked package reliabilityVSAvoidmanufacturing process simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The detection pads are formed on the chips during the chip manufacturing process itself, before stacking. This preliminary action integrates the measurement capability into the chip fabrication, so that when chips are stacked, the detection infrastructure is already in place and no additional complex manufacturing steps are needed later.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The detection pads serve multiple functions: they are part of the normal chip electrode structure and simultaneously serve as measurement points for stacking quality. This multi-functionality eliminates the need for separate dedicated measurement structures, simplifying the overall manufacturing process while enabling reliable detection.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If detection pads are added to chips, then stacking accuracy can be measured, but chip structure becomes more complex

Engineering Contradiction:

Improvejoint gap measurementVSAvoidchip pad structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the detection pads with the normal chip electrode structures. The same conductive elements that serve electrical functions in the chip also serve as detection pads for stacking measurement. This merging eliminates the need for separate detection structures and reduces overall chip structural complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The chip electrodes serve dual purposes: they are functional elements for the chip's operation and simultaneously serve as detection pads for measuring joint gaps and stacking accuracy. This universal use of existing structures avoids adding separate complexity to the chip design.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables accurate detection of stacking accuracy and joint gaps, ensuring high reliability of chip-stacked semiconductor packages through non-destructive capacitance measurements during the manufacturing process.

Implementation Method 1

the first test terminal and the second test terminal are configured to measure a capacitance between the second detection pad and the fourth detection pad

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11869818B2Chip-stacked semiconductor package and method of manufacturing same

Publication Date: 2024.01.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.