Chip Stack Clock Tree Layout for Low-Skew Leaf Routing
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Solution Overview
Problem
Existing clock tree routing in multi-chip devices experiences skew due to inter-wafer variation, which is not effectively addressed in current technologies.
Innovation Solution
Implementing in-chip routing of the clock tree within a single logical chip in a chip stack, using programmable leaf-level connection bridges that extend out-of-chip to connect leaf nodes across multiple chips, thereby reducing skew by containing routing within a unified logical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock tree routing is distributed across multiple chips in a chip stack, then device functionality and integration are improved, but clock signal skew increases due to inter-wafer variation
Solution Approach 1:
The clock tree routing is segmented into in-chip routing portions contained within a single logical chip and out-of-chip routing portions that connect different chips. This segmentation allows the clock signal to be routed through multiple chips while maintaining synchronization by keeping the critical in-chip routing portion isolated within one logical chip, thereby reducing skew caused by inter-wafer variation.
Solution Approach 2:
Leaf-level connection bridges serve as intermediaries that connect leaf nodes across different chips while maintaining the logical chip boundary for routing purposes. These bridges enable out-of-chip connectivity for functionality while preserving the in-chip routing containment that reduces clock skew.
2Manufacturing precision
If in-chip routing is contained within one logical chip, then clock signal skew is reduced, but device complexity increases due to leaf-level connection bridges extending through multiple chips
Solution Approach 1:
The routing structure is made dynamic and configurable through programmable leaf-level connection bridges that can be configured post-fabrication. This allows the system to adapt the routing paths to minimize skew while managing complexity through software control rather than fixed hardware structures.
Solution Approach 2:
The leaf-level connection bridges are programmable, allowing parameters such as routing paths and connection configurations to be changed after fabrication. This enables optimization of clock skew performance without requiring complex fixed hardware structures, managing device complexity through reconfigurability.
Data Source
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AI summary
Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips (102, 104, 106, 108). The chip stack includes a clock tree (902, 904). In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge (922, 924). The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.