Chip Stack Clock Tree Routing to Reduce Inter-Chip Skew
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Solution Overview
Problem
In multi-chip devices, clock signal skew is a significant issue due to inter-wafer variation, which can lead to performance degradation and increased manufacturing costs, as existing technologies struggle to integrate clock trees across multiple chips effectively.
Innovation Solution
Implementing in-chip routing of the clock tree within a single logical chip, where all branches of the clock tree have corresponding in-chip routing within the same physical chip, and using programmable leaf-level connection bridges to extend through multiple chips, ensuring that the clock signal is propagated with minimal skew by avoiding inter-wafer variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock tree routing is distributed across multiple physical chips, then device functionality and integration are improved, but clock signal skew increases due to inter-wafer variation
Solution Approach 1:
The clock tree is segmented into in-chip portions and inter-chip connection portions. The in-chip routing is contained within a single logical chip to maintain timing precision, while the connection bridges extend through multiple physical chips to enable distributed functionality. This segmentation allows the system to achieve both high functionality and low skew by keeping critical timing paths within one chip.
Solution Approach 2:
Leaf-level connection bridges serve as intermediaries between the in-chip clock tree routing and the distributed chip architecture. These bridges extend through multiple chips while maintaining electrical connection to the clock tree within a single logical chip, enabling clock signal distribution across multiple physical chips without introducing significant skew.
2Manufacturing precision
If in-chip routing is contained within one logical chip, then clock signal skew is reduced, but device complexity increases due to inter-chip connections
Solution Approach 1:
The routing architecture is segmented into in-chip portions (contained within one logical chip) and inter-chip connection portions (leaf-level connection bridges). This segmentation isolates the clock signal timing-critical paths within a single chip to minimize skew, while allowing functional distribution across multiple chips through the connection bridges.
Solution Approach 2:
The leaf-level connection bridges extend in the out-of-chip direction (vertical dimension) through multiple chips, while the in-chip routing remains in the planar dimension within a single logical chip. This dimensional separation allows the system to achieve both low skew (through in-chip containment) and distributed functionality (through out-of-chip extension).
Data Source
AI summary
Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.