Semiconductor Chip Stack Layout for CMP Dishing Control
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Solution Overview
Problem
The chemical mechanical polishing (CMP) process in semiconductor manufacturing faces challenges such as dishing and rounding, which can be exacerbated by the thinning and miniaturization of semiconductor systems, requiring innovative solutions for effective chip stacking and packaging.
Innovation Solution
A semiconductor chip stack structure is developed with a first semiconductor chip and a second semiconductor chip bonded in a die-to-wafer configuration, featuring redistribution layers, metal wires, and a molding member, where the metal wires are exposed after CMP processing to serve as reveal marks and provide heat dissipation and 3D electrical connections, thereby preventing dishing and rounding issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) process is used for planarization, then surface flatness is improved, but dishing and rounding defects occur
Solution Approach 1:
The patent applies preliminary action by forming a protective coating layer on the semiconductor chip surface before the CMP process. This coating layer is designed to prevent direct contact between the CMP abrasive and the underlying metal interconnect structures, thereby preventing dishing and rounding while still allowing the CMP process to achieve the desired surface flatness for the overlying dielectric layers.
Solution Approach 2:
The patent introduces an intermediary protective coating layer that acts as a mediator between the CMP process and the metal interconnect structures. This coating layer allows the CMP process to proceed for planarization while protecting the metal structures from harmful mechanical action, thus eliminating dishing and rounding defects.
2Productivity
If die-to-wafer bonding is used for chip stacking, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the manufacturing process into distinct stages: first forming the protective coating on each chip, then performing the die-to-wafer bonding, and finally removing the protective coating. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity while achieving high integration density through chip stacking.
Solution Approach 2:
The protective coating layer serves multiple functions: it protects metal structures during CMP, acts as a temporary placeholder during bonding alignment, and can be removed without damaging underlying structures. This multi-functionality simplifies the overall manufacturing process by using a single layer for multiple purposes, reducing the need for additional specialized process steps.
Data Source
AI summary
A semiconductor chip stack structure includes: a first semiconductor chip including a first semiconductor substrate, a first redistribution layer on the first semiconductor substrate and including a first redistribution pattern, and a first pad on an outermost side of the first redistribution layer; a second semiconductor chip including a second semiconductor substrate, a second redistribution layer on the second semiconductor substrate and including a second redistribution pattern, and a second pad on an outermost side of the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire on the first semiconductor chip; a second metal wire on the second semiconductor chip; and a molding member on the first semiconductor chip and at least a portion of each of the second semiconductor chip, the first metal wire, and the second metal wire.