Semiconductor Chip Stack Contact Structure Without Via Resistance
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric and reliability characteristics.
Innovation Solution
The semiconductor device incorporates a substrate with a logic cell region and a connection region, featuring a dummy transistor, an intermediate connection layer, an etch stop layer, and a penetration contact that protrudes above the etch stop layer, directly connecting to a first metal layer interconnection line without a via, reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent changes the physical parameters of the contact structure by extending the penetration contact to protrude above the etch stop layer, creating direct contact with the interconnection line. This structural parameter change compensates for the deteriorating operational properties caused by MOS-FET scaling, maintaining reliable electrical connection despite smaller device dimensions.
2Ease of manufacture
If a via is used to connect the penetration contact to the first metal layer, then manufacturing process is simplified, but electrical resistance increases
Solution Approach 1:
The patent extracts the via structure from the connection path between the penetration contact and the first metal layer. By removing the via, the patent achieves direct contact between the protruding penetration contact and the interconnection line, eliminating the additional electrical resistance that would be introduced by the via while still maintaining manufacturing feasibility.
3Reliability
If the penetration contact is extended to protrude above the etch stop layer, then direct contact with interconnection line is achieved reducing electrical resistance, but device complexity increases
Solution Approach 1:
The patent extends the penetration contact in the vertical dimension to protrude above the etch stop layer, creating direct contact with the interconnection line. This vertical extension in another dimension achieves the goal of reducing electrical resistance without significantly increasing horizontal device complexity, as the protrusion is along the existing vertical stack.
Data Source
AI summary
A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.