Chip-Stack Structure Direct Contact Conductor Pad
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Solution Overview
Problem
The production of 3D ICs faces challenges such as high cost and low yield due to complex manufacturing processes and details in wafer thinning and chip stacking.
Innovation Solution
A chip-stack structure and manufacturing method where the first contact conductor of the first chip is directly physically in contact with the second pad of the second chip, eliminating the need for additional connecting pads on the substrate surface, simplifying the process and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional connecting pads are formed on the substrate surface to connect contact conductors and pads, then reliable electrical connection is achieved, but the manufacturing process becomes complex and yield decreases
Solution Approach 1:
The patent extracts and eliminates the additional connecting pads from the substrate surface, allowing the contact conductor to directly contact the pad. This removes unnecessary manufacturing steps while maintaining reliable electrical connection through the direct contact between the exposed contact conductor and the pad.
Solution Approach 2:
Instead of forming pads on the substrate surface to connect to contact conductors, the patent inverts the approach by exposing the contact conductor directly on the substrate surface to contact the pad. This reversal eliminates the need for additional connecting pads and simplifies the manufacturing process.
2Reliability
If additional connecting pads are formed on the substrate surface, then electrical connection is established, but production cost increases
Solution Approach 1:
The patent extracts and eliminates the additional connecting pads from the substrate surface, allowing the contact conductor to directly contact the pad. This removes unnecessary manufacturing steps and material usage, thereby reducing production cost while maintaining reliable electrical connection.
3Productivity
If wafer thinning and chip stacking processes are performed with detailed manufacturing steps, then chip stacking is achieved, but production yield decreases
Solution Approach 1:
The patent inverts the conventional approach by exposing the contact conductor directly instead of forming additional pads. This simplification reduces manufacturing precision requirements and minimizes process variations, thereby improving production yield while maintaining chip stacking capability.
Solution Approach 2:
The contact conductor is prepared and positioned in advance within the substrate, exposed on the substrate surface before chip stacking. This preliminary action ensures proper alignment and contact between the contact conductor and pad, reducing the need for complex alignment processes and improving process yield.
Data Source
AI summary
A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.