Chip Stack Semiconductor Package With Exposed-Surface Interconnects
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compactness and high performance due to limitations in stacking semiconductor chips while maintaining efficient electrical connections and manufacturing yield.
Innovation Solution
A semiconductor package design that includes a substrate with a first semiconductor chip and multiple second semiconductor chips stacked on top, each with the same size and storage capacity as the first chip, connected via bonding wires and connectors, allowing for compact size and high yield fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase storage capacity, then the package density improves, but the electrical connection complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking, placing second semiconductor chips on top of first semiconductor chips. This vertical arrangement increases storage capacity while managing connection complexity through structured interlayer connectors
Solution Approach 2:
The patent divides the semiconductor package into multiple layers with first semiconductor chips at the bottom, second semiconductor chips stacked above, and intermediate connectors facilitating electrical connections between layers. This segmentation allows independent optimization of each layer's function
2Quantity of substance
If multiple semiconductor chips are stacked to increase storage capacity, then the package density improves, but the manufacturing yield decreases
Solution Approach 1:
The patent incorporates connectors and bonding structures during the chip stacking process itself, rather than adding them later. This preliminary integration of connection elements enables easier assembly and higher manufacturing yield when stacking multiple chips
Solution Approach 2:
The patent places second semiconductor chips on top of first semiconductor chips, creating a nested vertical structure. This nesting approach maximizes space utilization while maintaining manageable manufacturing complexity through standardized stacking procedures
3Volume of moving object
If second semiconductor chips are placed on top of first semiconductor chips, then the package size reduces, but the electrical connection reliability becomes more difficult to ensure
Solution Approach 1:
The patent introduces connectors as intermediary elements between first and second semiconductor chips. These connectors facilitate reliable electrical connections across layers, ensuring signal integrity while enabling the compact stacked configuration
Solution Approach 2:
The patent combines multiple semiconductor chips and connectors into a single integrated stacked structure. This merging approach reduces overall package volume while maintaining connection reliability through unified assembly and standardized interfaces
Data Source
AI summary
A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.