Chip Stack Package Selective Chip Extraction
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Solution Overview
Problem
Conventional chip stack packages have lower test efficiency and require discarding all semiconductor chips when one is defective, due to the molding compound, leading to wastage of functional chips.
Innovation Solution
A chip stack package design with a substrate, semiconductor chips, a molding member, and a controller that allows selective identification and extraction of operable chips, using a selection chip to determine and display the status of each chip, enabling the use of the package even if one chip is defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are molded with a molding member (epoxy molding compound), then the chip stack package is protected and structurally stable, but the defective semiconductor chip cannot be removed without breaking the molding member and damaging the chip stack package
Solution Approach 1:
The chip stack package is divided into separable components: the molding member is designed to allow selective removal of individual semiconductor chips without breaking the entire package structure. The bonding between chips and molding member is engineered to be removable through controlled processes, enabling segmentation of the package for repair purposes.
Solution Approach 2:
The defective semiconductor chip is extracted from the chip stack package while leaving the molding member and other functional chips intact. This extraction is achieved through controlled processes that remove only the defective chip without damaging the surrounding structure, allowing the package to be repaired and reused.
2Measurement precision
If all semiconductor chips are tested individually, then the defective chip can be identified, but the test efficiency is lower compared to testing a single chip
Solution Approach 1:
Multiple semiconductor chips are electrically connected in parallel to form a single functional unit that can be tested as one integrated system. The chip stack package is designed with shared electrical pathways and control circuits that allow simultaneous testing of all chips, combining their functions to achieve efficient bulk testing while maintaining individual chip functionality.
Solution Approach 2:
The chip stack package incorporates a universal testing interface and control mechanism that can test multiple chips simultaneously through a single test connection. The electrical connection structure is designed to provide universal access points for testing any or all chips in the stack, eliminating the need for separate test setups for each chip.
3Reliability
If a defective semiconductor chip is detected in the chip stack package, then the package is considered defective, but this results in discarding all semiconductor chips including the functional ones
Solution Approach 1:
The defective semiconductor chip is selectively extracted and removed from the chip stack package, while the functional chips remain intact and continue to operate. This extraction process allows the package to be repaired by replacing only the defective chip, thereby preventing waste of functional chips and reducing material loss.
Solution Approach 2:
Only the defective semiconductor chip is discarded, while the functional chips and the molding member are recovered and reused. The package structure is designed to facilitate recovery of valuable components, allowing the majority of the package to be salvaged and reused after removing and replacing only the defective element.
Data Source
AI summary
A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips.