Chip Stack Inductor Structure for Semiconductor Package Noise Reduction
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Solution Overview
Problem
As semiconductor packages become more densely integrated and miniaturized, they face challenges with electromagnetic signal interference, which reduces performance and efficiency due to the limited effectiveness of external inductors in noise reduction and increased space requirements.
Innovation Solution
A semiconductor package structure is designed with a chip stack structure where first conductive plug sets in each chip are connected through a wire structure to form an inductor, reducing communication noise and improving quality without the need for external inductors, thereby increasing integration density and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If external inductors are used for noise reduction, then communication noise is reduced, but additional space is occupied and integration density is limited
Solution Approach 1:
The patent merges the inductor function with the existing chip stack structure by using conductive plugs and wire structures that are already present in the packaging architecture. This integration eliminates the need for separate external inductors while maintaining noise reduction functionality, thereby resolving the space occupation contradiction.
Solution Approach 2:
The conductive plug sets and wire structures serve dual purposes: they provide electrical connection between chips and simultaneously function as inductors for noise reduction. This multi-functionality allows the same structural elements to fulfill multiple roles, eliminating the need for additional space-dedicated components.
2Quantity of substance
If chip density is increased through miniaturization, then integration level is improved, but electromagnetic signal interference increases
Solution Approach 1:
The patent converts the harmful electromagnetic interference into a beneficial effect by utilizing the wire structures and conductive plugs as inductors. These same structural elements that enable high-density interconnection also provide noise reduction functionality, turning the potential harm of miniaturization into a benefit for electromagnetic compatibility.
3Volume of moving object
If inductor size is reduced to fit miniaturized packages, then package size is reduced, but noise reduction effectiveness decreases
Solution Approach 1:
The patent implements noise reduction locally at each chip stack location by integrating inductors directly into the chip stack structure. This localized approach allows effective noise reduction to be achieved at the source without requiring large external inductors, thereby maintaining noise reduction effectiveness while accommodating miniaturized package sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The inductor structure formed within the chip stack effectively reduces communication noise, enhances signal-to-noise ratio, and allows for increased integration density and miniaturization of the semiconductor package without occupying additional space.
Implementation Method 1
the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure
Data Source
AI summary
The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.