Chip Stack Interconnect Layout for Signal Integrity and Lower Power
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Solution Overview
Problem
The existing semiconductor package technologies face challenges in efficiently transmitting and receiving signals between stacked chips due to limitations in scaling down and integration, leading to increased power consumption and reduced signal integrity.
Innovation Solution
A semiconductor package with a chip stack structure that includes a substrate, a master chip, and a slave chip stacked on the substrate, each with specific pads and buffers for command/address and data transmission, connected by bonding wires to improve signal transmission and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked vertically to increase integration density, then the degree of integration is improved, but signal transmission quality and power consumption become problematic
Solution Approach 1:
The patent segments the signal transmission paths by introducing separate dedicated transmission lines for command/address signals and data signals between stacked chips. This segmentation allows independent optimization of each signal type, improving overall signal integrity while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent introduces intermediary buffering structures and impedance matching layers between stacked chips to mediate signal transmission. These intermediaries reduce signal reflections and distortions that occur in vertical chip stacks, thereby maintaining signal quality despite the increased integration density.
2Productivity
If chips are stacked vertically to increase integration density, then the degree of integration is improved, but power consumption increases
Solution Approach 1:
The patent segments power delivery paths into separate dedicated lines for different functional blocks (command/address vs. data). This segmentation reduces cross-talk and signal interference, allowing for more efficient power management and reduced overall power consumption in the vertically stacked configuration.
Solution Approach 2:
The patent optimizes transmission line impedance parameters and signal voltage levels specifically for vertical chip stack configurations. By adjusting these parameters, the patent reduces power consumption while maintaining signal integrity in the high-density stacked architecture.
3Productivity
If scale-down method is used to improve integration, then line widths are reduced, but the scaling technology reaches its limits
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. This dimensional change allows continued integration improvement without further reducing line widths, thereby avoiding the manufacturing precision limits of scale-down technology while achieving higher integration densities.
Data Source
AI summary
An embodiment of the disclosed technology provides a semiconductor package including: a substrate; a first chip and a second chip stacked on the substrate, each of the first chip and the second chip including a slice command/address reception pad, a slice command/address transmission pad, a slice data pad, an input buffer connected to the slice command/address reception pad, an output buffer connected to the slice command/address transmission pad and an input/output buffer connected to the slice data pad; a first connection member connecting the slice command/address transmission pad of the first chip to the slice command/address reception pad of the second chip; and a second connection member connecting the slice data pad of the first chip to the slice data pad of the second chip.