Chip Stack Locking Through Vias for Secure Data Isolation
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Solution Overview
Problem
Conventional semiconductor chip stacks using traditional through-silicon vias (TSVs) pose a security risk due to their bus-like nature, allowing data snooping by malicious chips, and lack effective compartmentalization of data flow, which can lead to unauthorized access and data breaches.
Innovation Solution
Implementing through-silicon field effect transistors (TFETs) and encryption/decryption circuits to selectively control data transmission and encryption, ensuring secure data flow by compartmentalizing data pathways and encrypting data before transmission, thereby preventing unauthorized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional through-silicon vias (TSVs) are used for data transmission between chips, then data transmission is simple and direct, but security is compromised due to bus-like nature allowing data snooping
Solution Approach 1:
The patent segments the data transmission pathway by replacing traditional through-silicon vias with through-silicon field effect transistors (TFETs). Each TFET acts as an independent controllable channel, dividing the shared bus into isolated segments that can be individually locked. This segmentation prevents unauthorized chips from snooping data intended for specific destinations while maintaining transmission efficiency.
Solution Approach 2:
The patent introduces gate control circuits as intermediaries between data sources and destinations. These control circuits manage the locking and unlocking of TFET channels, mediating data flow to ensure only authorized recipients can access transmitted data. The intermediary layer adds security without significantly increasing overall system complexity.
2Reliability
If data is transmitted openly through aligned TSVs, then transmission speed is high, but unauthorized access and data breaches occur
Solution Approach 1:
The patent divides the monolithic data bus into multiple segmented channels, each controlled by dedicated TFETs and gate circuits. This compartmentalization isolates data streams so that unauthorized access to one channel does not compromise others, maintaining data integrity while enabling selective transmission to different destinations.
Solution Approach 2:
The patent applies different functional properties to different parts of the data transmission system. Each TFET channel has localized control capabilities, allowing specific segments to be locked or unlocked based on destination requirements. This local quality control ensures data integrity for each transmission path without affecting overall system performance.
3Productivity
If conventional TSV alignment is used for efficient data bus operation, then productivity is high, but security risks from data snooping increase
Solution Approach 1:
The patent transforms the static, always-open TSV data bus into a dynamic system where TFET channels can be selectively locked or unlocked in real-time. This dynamic control allows the system to maintain high transmission efficiency for authorized data flows while simultaneously blocking unauthorized access, resolving the contradiction between productivity and security.
Solution Approach 2:
The patent implements periodic locking and unlocking cycles of TFET channels based on transmission requirements. During active transmission periods, channels are unlocked for efficient data flow; during idle or secure periods, channels are locked to prevent snooping. This periodic action maintains productivity while mitigating security risks.
Data Source
AI summary
Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.