Chip Stack Without Carrier for Thin Packaging
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Solution Overview
Problem
Conventional stacked chip structures face challenges in reducing thickness, leading to increased volume and design limitations due to the presence of package carriers and solder balls, which restricts package integration and thermal management.
Innovation Solution
A thickness-reduced stacked structure is achieved by eliminating the circuit carrier and using an insulation layer with conductive elements to connect chips, allowing for direct attachment and encapsulation of chips within the insulation layer, along with solder balls for external connections, enabling improved heat radiation and reduced material and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacked chip structure with package carrier and solder balls is used, then electrical connectivity and structural support are achieved, but thickness and volume increase sharply
Solution Approach 1:
The patent removes the package carrier from the conventional stacked chip structure, extracting only the essential functional elements (chips and interconnection structures) to reduce overall thickness while maintaining electrical connectivity through alternative means such as direct chip-to-chip bonding or simplified interconnection layers
Solution Approach 2:
The patent transitions from traditional vertical stacking with thick interconnection layers to a more compact three-dimensional arrangement where chips are positioned closer together with reduced spacing, utilizing advanced interconnection techniques that enable thinner overall structure while preserving electrical pathways
2Strength
If package carrier and multiple interconnection layers are used, then structural support and electrical connectivity are maintained, but device complexity increases
Solution Approach 1:
The patent merges the functions of the package carrier and interconnection structures into a more integrated configuration, where structural support and electrical connectivity are achieved through combined elements rather than separate components, thereby reducing overall structural complexity
Solution Approach 2:
The patent designs interconnection structures that simultaneously provide both structural support and electrical connectivity functions, eliminating the need for separate dedicated support structures and simplifying the overall package architecture
3Stability of the object's composition
If conventional stacked structure with fixed thickness is used, then manufacturing stability is maintained, but package integration is restricted
Solution Approach 1:
The patent employs adjustable design parameters in the interconnection structures and chip positioning systems, allowing optimization of both thickness and integration level according to specific application requirements while maintaining manufacturing stability through controlled parameter ranges
Data Source
AI summary
A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip includes a first contact disposed on an active surface of the second chip. The insulation layer disposed on the active surface of the first chip encapsulates the second chip. The first conductive element is formed in the insulation layer for electrically connecting one end of the first conductive element to the first contact and the other end of the first conductive element exposed outside the insulation layer. A wafer structure for making the stacked structure of chips is also provided. The stacked structure of chips has no circuit carrier, hence reducing the thickness of the stacked structure.