Semiconductor Chip Stack Penetration Contact Layout for Low Resistance
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric and reliability characteristics.
Innovation Solution
A semiconductor device structure that includes a substrate with a logic cell region and a connection region, featuring a dummy transistor, an intermediate connection layer, a first metal layer, an etch stop layer, and a penetration contact that extends from the first metal layer toward the substrate, reducing electrical resistance and improving contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOS-FET structures to three-dimensional stacked chip architectures. By stacking multiple semiconductor chips vertically and forming penetration contacts that extend through the substrate thickness, the invention utilizes the third dimension (vertical direction) to increase device density without further reducing the lateral pattern size, thereby maintaining operational properties while achieving higher integration.
Solution Approach 2:
The patent implements a stacked chip structure where multiple semiconductor chips are nested vertically one on top of another. The penetration contacts are formed to extend through the substrate and connect interconnection lines between different stacked chips, creating a nested hierarchical interconnection system that maintains signal integrity while achieving high-density integration.
2Area of stationary object
If penetration contact extends through substrate to connect interconnection lines, then contact area is increased, but manufacturing complexity increases
Solution Approach 1:
The patent forms penetration contacts that extend through the substrate before final interconnection line formation. The etch stop layer is positioned to cover the top surface of the connection pattern, and the penetration contact is pre-formed to protrude above the etch stop layer, enabling subsequent interconnection lines to be directly formed on the penetration contact surface. This preliminary formation simplifies the overall manufacturing process by establishing the vertical connection pathway early in the fabrication sequence.
Solution Approach 2:
The etch stop layer serves as an intermediary element between the intermediate connection layer and the first metal layer. It covers the top surface of the connection pattern and provides a controlled interface for the penetration contact, facilitating precise alignment and connection while simplifying the etching and formation processes of subsequent interconnection structures.
Data Source
AI summary
A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.