Chip Stack Package Plug Formation via Substrate Merging
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Solution Overview
Problem
Conventional chip stack package manufacturing methods face challenges such as increased time for plating processes, void generation, and non-uniform plug shape and size, leading to alignment issues and contact problems between chips.
Innovation Solution
A chip stack package design featuring a substrate with a wiring pattern and seed layer, where each chip has a first through-hole aligned on the seed layer, with adhesive layers having second through-holes that connect to the first, allowing a plug to fill and electrically connect the chips, reducing void generation and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plugs are formed in each chip by plating process, then electrical connection between chips is achieved, but manufacturing time is greatly increased and voids are generated
Solution Approach 1:
The patent merges the plug formation process from individual chip-level operations to substrate-level operation. Instead of forming plugs in each chip separately through time-consuming plating processes, a single plug is formed on the substrate that connects multiple chips simultaneously, greatly reducing manufacturing time while maintaining electrical connection reliability
Solution Approach 2:
The substrate serves as an intermediary element that facilitates electrical connection between multiple chips. Rather than directly connecting chips to each other through individual plugs, the substrate acts as a central hub with a single plug that distributes electrical connections to multiple chips, reducing the total number of plating operations required
2Reliability
If plugs are formed in each chip, then electrical connection is established, but uniformity of plug shape and dimensions is deteriorated
Solution Approach 1:
By combining multiple chip connections into a single plug formation process on the substrate, the patent ensures uniform plug shape and dimensions. The single plug is formed through one controlled plating operation rather than multiple separate operations, eliminating variations in plug geometry that occur when each chip is processed independently
3Reliability
If solder is coated on protruding plug, then electrical connection is enhanced, but chip alignment accuracy is reduced
Solution Approach 1:
The patent inverts the conventional approach by forming the plug on the substrate rather than on the chip. This reversal allows the plug to remain stationary on the substrate while chips are aligned to it, eliminating the alignment problems caused by protruding solder on movable chip surfaces
Solution Approach 2:
The substrate with its centrally formed plug acts as a stable intermediary reference point for chip alignment. Multiple chips can be precisely positioned relative to this fixed plug location, ensuring accurate alignment without the complications of coating solder on protruding plug structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes voids in the plug, enhances plug uniformity, reduces manufacturing time, and ensures accurate chip stacking and electrical connectivity, even with varying chip sizes and shapes.
Implementation Method 1
each of the recesses is filled up with a conductive material by a plating process to form a plug in the recesses
Data Source
AI summary
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.