Semiconductor Chip Stack Resin Support Without Spacer Chips
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Solution Overview
Problem
The existing package structure of semiconductor devices, which includes a spacer chip to support memory chips stacked above a controller chip, increases assembly costs and process complexity, and poses challenges in maintaining matching heights, leading to deteriorated mold-filling properties and wettability issues.
Innovation Solution
A semiconductor device configuration that eliminates the need for a spacer chip by using a resin layer to support both the controller and memory chips, where the resin layer covers the connection bumps and extends beyond the outer edges of the memory chips, ensuring appropriate support and alignment without the need for additional spacer components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spacer chip is used to support memory chips, then the memory chips can be stacked above the controller chip, but the assembly cost and number of processes increase
Solution Approach 1:
The invention extracts and removes the spacer chip from the package structure, replacing it with a support structure formed directly on the controller chip. This eliminates the need for additional spacer components while maintaining the stacking capability of memory chips above the controller chip.
Solution Approach 2:
The invention merges the support function previously performed by the spacer chip with the controller chip itself. The support structure is integrated into the controller chip package, combining multiple functions (controller operation and mechanical support) into a single component, thereby reducing overall assembly complexity.
2Reliability
If a spacer chip is used to support memory chips, then the memory chips can be stacked, but the matching heights between controller chip and spacer chip becomes challenging
Solution Approach 1:
The invention removes the spacer chip that caused height matching challenges and replaces it with a support structure of controlled thickness formed on the controller chip. This allows precise control of the support height to match the memory chip thickness, eliminating alignment issues.
Solution Approach 2:
The invention changes the parameter of support structure thickness to precisely match the memory chip thickness. By controlling the thickness of the support structure formed on the controller chip, the invention achieves accurate height matching without the complexity of coordinating multiple chip heights.
3Reliability
If the height matching between controller chip and spacer chip is not precise, then a step is generated, but the wettability of the memory chip deteriorates
Solution Approach 1:
The invention removes the spacer chip that created step formations and replaces it with an integrated support structure on the controller chip. This eliminates the step between spacer and controller chips, ensuring uniform surface for memory chip bonding and maintaining wettability.
Solution Approach 2:
The invention uses an asymmetric support structure design where the support is formed only in specific regions where needed, allowing the memory chip to sit flush with the controller chip surface while maintaining proper bonding surface area and wettability.
Data Source
AI summary
A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.