Chip Stack Interconnect Structure for Dense 3D Packaging
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Solution Overview
Problem
Existing chip stack package manufacturing methods face challenges in achieving high-density stacking of semiconductor chips while maintaining efficient electrical connectivity and minimizing package height.
Innovation Solution
The method involves stacking semiconductor chips with exposed side surfaces of connecting patterns and forming conductive pillars to connect these patterns, followed by recessing the semiconductor substrates and covering with a second dielectric layer to fill spaces and isolate conductive pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in three dimensions to reduce package size, then the package density and capacity are improved, but the manufacturing complexity and difficulty of achieving efficient electrical connectivity increase
Solution Approach 1:
The connecting pattern is divided into multiple sections: a first section within the dielectric layer and a second section extending to the side surface. This segmentation allows conductive pillars to connect to specific portions of the connecting pattern, simplifying the three-dimensional interconnection process while maintaining high stacking density
Solution Approach 2:
The connecting pattern extends not only horizontally within the dielectric layer but also vertically to the side surface of the dielectric layer. This dimensional extension enables conductive pillars to establish electrical connections through side-surface contact, reducing manufacturing complexity in three-dimensional chip stacking
2Reliability
If conductive pillars are formed to connect stacked chips, then electrical connectivity is improved, but the package height increases
Solution Approach 1:
The second section of the connecting pattern is embedded within the recessed region of the upper semiconductor chip, with the conductive pillar nested around it. This nested structure allows electrical connection without adding significant height, as the connecting pattern and conductive pillar occupy the same vertical space rather than stacking sequentially
Solution Approach 2:
Instead of extending conductive pillars upward from the base to connect chips, the connecting pattern extends downward from the dielectric layer side surface to meet the conductive pillar. This inverted approach reduces package height by utilizing the recessed region of the upper chip
3Length of stationary object
If semiconductor substrates are recessed to reduce package height, then the package compactness is improved, but the insulation and isolation of conductive pillars become more difficult
Solution Approach 1:
The dielectric layer is selectively recessed only in specific regions where conductive pillars are located, while maintaining full coverage in other areas. This localized recessing provides precise insulation where needed (around conductive pillars) while reducing package height in critical regions, maintaining reliable electrical isolation
Solution Approach 2:
The dielectric layer acts as an intermediary material that fills the recessed region and provides insulation between the conductive pillar and the semiconductor substrate. This intermediary structure ensures reliable electrical isolation while enabling the compact recessed design
Data Source
AI summary
A chip stack package and a method of manufacturing the same are described. Semiconductor chips each including a semiconductor substrate, a first dielectric layer, and a connecting pattern are stacked. The connecting pattern is formed positioned within the first dielectric layer and has a first side surface along a side surface of the stacked semiconductor chips. Conductive pillars are formed connected to a plurality of the first side surfaces of the connecting patterns of the stacked semiconductor chips, connecting the stacked semiconductor chips to each other. The semiconductor substrates are recessed from the second side surfaces of the first dielectric layer. A second dielectric layer is formed to cover the conductive pillars and to fill spaces between the recessed semiconductor substrates and the conductive pillars.