Chip Stack Testing Tray With Adhesive Alignment
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Solution Overview
Problem
Existing chip stack device testing methods face challenges in accurately and efficiently testing multiple chip stack devices with different external sizes due to alignment issues and high costs associated with dedicated trays and units, which require frequent maintenance and production changes.
Innovation Solution
A chip stack device testing method utilizing a sheet tray with an adhesive layer, matching the shape and dimensions of an undiced substrate, to align and support chip stack devices, allowing for simultaneous testing with a rearranging unit that transfers devices to the tray for precise alignment and testing, similar to a wafer process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip stack devices with different external sizes are disposed in a tray for testing, then multiple devices can be tested simultaneously, but the contact pads cannot be aligned with the probes due to position variations
Solution Approach 1:
A tray cover is introduced as an intermediary component between the chip stack devices and the probes. The tray cover includes positioning protrusions that engage with positioning recesses on the tray, establishing a precise reference coordinate system. This intermediary structure ensures that regardless of variations in chip stack device sizes, the contact pads are consistently positioned relative to the probes through the tray cover's reference framework, enabling both simultaneous testing of multiple devices and precise alignment.
2Manufacturing precision
If dedicated trays with high accuracy processing are used, then alignment precision is improved, but the cost increases and dedicated trays need to be produced for each device type
Solution Approach 1:
The tray and tray cover are designed as universal components that can accommodate multiple device types. The positioning protrusions and recesses create a standardized reference system that works with various chip stack device configurations. This universal design eliminates the need to produce dedicated trays for each device type, reducing manufacturing costs while maintaining high alignment precision through the standardized positioning mechanism.
3Manufacturing precision
If chip stack devices are tested one by one using existing trays, then alignment is maintained, but the testing time increases and operation efficiency decreases
Solution Approach 1:
The tray cover integrates multiple positioning protrusions that simultaneously align multiple chip stack devices with the probe array. By merging the alignment function into the tray cover structure, multiple devices can be positioned and tested in parallel without sacrificing alignment precision. This eliminates the need for sequential testing, significantly reducing total testing time while maintaining the same alignment accuracy as single-device testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate and efficient testing of multiple chip stack devices with varying sizes at a lower cost, reducing the need for dedicated units and improving operational efficiency by maintaining alignment and thermal expansion compatibility.
Implementation Method 1
using a tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test and having an adhesive layer on a surface, attaching and supporting one or a plurality of the chip stack devices to the adhesive layer of the tray
Data Source
AI summary
A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.