Chip Stack Structure with External Vertical Conductive Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the volume of electric products, necessitating improved package designs to accommodate smaller and more compact semiconductor elements.
Innovation Solution
A chip stack structure is formed using a vertical conductive line positioned outside the projection area of chips, electrically connecting multiple chips and allowing for reduced horizontal and vertical distances between them, thereby minimizing package volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package technology is used, then chips can be mounted on package substrate, but the volume of electric products cannot be reduced sufficiently
Solution Approach 1:
The patent transitions from conventional planar chip mounting to a three-dimensional vertical stacking architecture. Multiple chips are stacked vertically and connected through vertical conductive lines, enabling space utilization in the vertical dimension rather than only horizontal expansion. This dimensional change directly reduces the overall volume of electric products while maintaining functional requirements.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked one above another, with each chip containing functional elements and being interconnected through vertical conductive lines. The chips are positioned within a compact footprint area, creating a nested arrangement that maximizes space utilization and reduces product volume.
2Volume of moving object
If chips are stacked vertically to reduce volume, then package size decreases, but current path length and heat dissipation become challenging
Solution Approach 1:
The patent introduces vertical conductive lines that extend through the stacked chip structure, providing direct current pathways in the vertical dimension. This vertical connectivity reduces current path length compared to horizontal routing, improving electrical performance while maintaining the compact vertical stacking architecture.
3Reliability
If vertical conductive lines are formed inside chip projection area, then electrical connection is achieved, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent extracts the vertical conductive lines from the chip projection area and positions them in the surrounding area. This separation allows the conductive lines to be formed independently without requiring precise alignment with chip features, significantly reducing manufacturing complexity and alignment precision requirements while maintaining reliable electrical connections between stacked chips.
Data Source
AI summary
A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip.