Chip Stack Via Layout for Low-Parasitic Signal Transmission
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges such as large parasitic capacitance and resistance in connection structures between chips, affecting signal transmission quality.
Innovation Solution
A memory chip and logic chip design with a global signal region and conductive via groups, where each conductive via group includes four normal conductive vias and redundant vias, allowing for efficient signal transmission and redundancy repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked using bonding process to form three-dimensional semiconductor device, then storage electron density increases and production cost per unit memory cell decreases, but parasitic capacitance and parasitic resistance in connection structures increase, affecting signal transmission quality
Solution Approach 1:
The patent divides the connection structure into multiple segments by introducing intermediate connection layers and distributing connection points across different levels. The conductive vias are segmented into multiple groups at different depths, with intermediate connection layers providing staged connections between stacked chips, thereby reducing the parasitic capacitance and resistance of individual connection paths while maintaining high storage density through multi-level stacking.
2Productivity
If conventional bonding process is used to stack chips, then three-dimensional device structure is achieved, but connection structures have large parasitic capacitance and large parasitic resistance
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the connection structure. Intermediate connection layers use materials with optimized electrical properties for specific connection depths, while conductive vias are distributed with varying densities and dimensions across different regions. This local optimization reduces parasitic effects in critical signal paths while maintaining overall three-dimensional stacking efficiency.
Data Source
AI summary
The present disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. In a global signal region of the logic chip, a plurality of conductive via groups are provided, where four normal conductive vias in an ith conductive via group are electrically connected in one-to-one correspondence to four internal ports in an ith internal port group, and a correspondence relationship between the four normal conductive vias and the four internal ports is determined based on a select signal.