Stacked Semiconductor Package Assembly for Void-Free Chip Bonding
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving structural reliability and effective heat dissipation while maintaining high integration and speed, especially in stacked semiconductor chip configurations.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip, a chip stacked structure with multiple second semiconductor chips bonded by metal-metal bonding, a third semiconductor chip with a dummy chip and pad patterns, and an adhesive layer that surrounds the pad patterns and fills voids between the stacked structure and the third semiconductor chip, all encapsulated within a molding layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If stacked semiconductor chips are used to achieve high integration, then device functionality is improved, but structural reliability deteriorates due to void formation at bonding interfaces
Solution Approach 1:
An adhesive layer is introduced as an intermediary substance between the chip stacked structure and the third semiconductor chip. This adhesive layer fills the void at the bonding interface, mediating the connection between the stacked chips and ensuring reliable bonding while maintaining the high integration benefit of the stacked configuration.
2Adaptability or versatility
If stacked semiconductor chips are used to achieve high integration, then device functionality is improved, but heat dissipation deteriorates
Solution Approach 1:
The adhesive layer serves as a thermal intermediary that fills voids at bonding interfaces. By eliminating air gaps (which are poor thermal conductors), the adhesive layer creates continuous thermal pathways that enable effective heat dissipation from the stacked semiconductor chips while preserving the high integration architecture.
Solution Approach 2:
The pad pattern on the third semiconductor chip is designed with specific geometric parameters (size, shape, distribution) to optimize thermal conduction. By adjusting these parameters, the heat dissipation performance is improved while maintaining the stacked chip configuration for high integration.
3Reliability
If adhesive layer is applied between chip stacked structure and third semiconductor chip, then structural reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The adhesive layer is applied in advance to the chip stacked structure or the third semiconductor chip before the bonding process. This preliminary action ensures that the adhesive is properly positioned and distributed, filling potential voids before final bonding occurs, thereby simplifying the overall manufacturing process while ensuring reliable structural bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances structural reliability by preventing void formation at bonding interfaces and improves heat dissipation through the pad patterns, thereby maintaining high integration and speed while ensuring reliable operation.
Implementation Method 1
an adhesive layer between the chip stacked structure and the third semiconductor chip
Implementation Method 2
a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips bonded to each other by metal-metal bonding
Data Source
AI summary
Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.