Chip Stack Structure With Stress Compensation Against Thin-Chip Warpage
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Solution Overview
Problem
The warpage of thin semiconductor chips in multi-chip packages leads to deteriorating leakage current characteristics, which is a challenge in achieving both thin thickness and high reliability.
Innovation Solution
A semiconductor package design that includes a stress compensation layer on the backside of thinner chips to offset internal stress, preventing warpage and improving leakage current characteristics, with a method involving wafer polishing and stress compensation layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the thickness of semiconductor chips is reduced to achieve high capacity and high performance, then the thickness of the entire package is reduced, but the stacked semiconductor chips warp due to their thin thickness, leading to deteriorating leakage current characteristics
Solution Approach 1:
The patent applies parameter changes by modifying the stress state of the chip substrate through forming a stress compensation layer. The internal stress of the chip substrate is changed from an unbalanced state causing warpage to a balanced state where the stress compensation layer offsets the internal stress, thereby preventing warpage while maintaining thin thickness
Solution Approach 2:
The patent uses composite materials by combining the chip substrate with a stress compensation layer to create a composite structure. This composite structure integrates two materials with different stress properties, where the stress compensation layer compensates for the internal stress of the chip substrate, preventing warpage without increasing overall thickness
2Length of stationary object
If the thickness of semiconductor chips is reduced, then the package thickness is reduced, but warpage occurs due to internal stress in the thin chips
Solution Approach 1:
The patent changes the stress parameter of the chip structure by introducing a stress compensation layer with controlled internal stress. This layer modifies the overall stress distribution in the thin chip, counteracting the internal stress that causes warpage and maintaining planarity
Solution Approach 2:
The stress compensation layer acts as a counterweight to the internal stress in the chip substrate. By positioning this layer with appropriate stress characteristics, it balances the internal stress forces, preventing warpage in the thin semiconductor chip
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a semiconductor package with reduced warpage and improved leakage current characteristics, ensuring high reliability and thin thickness by using stress compensation layers to counteract internal stress in thinner chips.
Implementation Method 1
a stress compensation layer on the second surface and having an internal stress that offsets an internal stress of the chip substrate
Data Source
AI summary
A semiconductor package includes a package substrate, a chip stack structure on the package substrate, the chip stack structure including a base chip having a first thickness and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness, and a sealing member on an upper surface of the package substrate and on the chip stack structure. At least one of the plurality of upper chips includes a chip substrate having opposite first and second surfaces, a circuit layer on the first surface, and a stress compensation layer on the second surface and having an internal stress that offsets a warpage of the chip substrate.