Chip Stack Mold Structure to Prevent Semiconductor Package Warpage
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Solution Overview
Problem
The increasing demand for high-performance, compact electronic components in portable devices poses challenges in reducing the size and weight of semiconductor packages, where the use of multiple adhesive members leads to technical issues such as structural instability and warpage due to thermal expansion.
Innovation Solution
A semiconductor package design featuring a stack of semiconductor chips with non-conductive layers filling spaces between adjacent chips and a mold layer that encloses the chip stack, eliminating non-conductive layers between the first and third semiconductor chips to prevent protrusion and warpage, thereby enhancing structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple adhesive members are used to attach components, then components can be securely mounted, but structural instability and warpage occur due to thermal expansion
Solution Approach 1:
The patent merges the functions of multiple adhesive members into a single adhesive layer formed by reflowing adhesive material. This consolidation eliminates the cumulative thermal expansion effects that caused warpage while maintaining secure attachment of semiconductor chips to the substrate, thereby resolving the contradiction between attachment strength and structural stability.
Solution Approach 2:
The patent changes the physical state and distribution of the adhesive material by applying heat to melt and redistribute it into a uniform layer. This parameter change (from discrete adhesive members to a continuous adhesive layer) eliminates gaps and reduces thermal expansion differential, simultaneously achieving strong attachment and structural stability.
2Strength
If adhesive members are placed between chips, then chips can be attached, but protrusion occurs leading to warpage
Solution Approach 1:
The patent combines multiple adhesive members into a single continuous adhesive layer that uniformly fills the space between chips and substrate. This merging eliminates protrusions that would otherwise cause warpage, while the adhesive layer maintains secure chip attachment through its continuous bonding interface.
Solution Approach 2:
The adhesive layer is applied with locally optimized properties - it fills gaps between chips and substrate while maintaining a uniform thickness that prevents protrusion. The local quality of the adhesive (uniform distribution, appropriate viscosity after reflow) ensures both attachment strength and package flatness without warpage.
3Reliability
If spaces between chips are filled with non-conductive layers, then electrical insulation is provided, but the number of layers increases leading to complexity
Solution Approach 1:
The patent merges the electrical insulation function with the adhesive layer itself. The adhesive material provides both mechanical bonding and electrical insulation properties, eliminating the need for separate non-conductive layers. This consolidation reduces the total number of layers while maintaining reliable electrical insulation between adjacent chips.
Solution Approach 2:
The adhesive layer performs multiple functions simultaneously: it provides mechanical attachment, fills spaces between chips, and provides electrical insulation. This multi-functionality eliminates the need for separate dedicated insulation layers, reducing structural complexity while maintaining all necessary functions.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.