Chip Stack Sealing Structure to Minimize Semiconductor Warpage
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Solution Overview
Problem
The semiconductor device experiences warpage due to differences in thermal expansion coefficients between the sealing insulation layer and adhesive layers, leading to issues like displacement and deformation during the sealing process.
Innovation Solution
The semiconductor device incorporates a resin area extending between the wiring board and the chip stack to reduce the shrinkage percentage difference between the sealing insulation layer and adhesive layers, and uses adhesive layers with varying thicknesses to prevent contact between bonding wires and semiconductor chips, along with a conductive shield layer to manage electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealing insulation layer is provided over a chip stack including multiple semiconductor chips, then the chips are electrically connected and sealed, but warpage and deformation occur due to differences in thermal expansion coefficients between the sealing insulation layer and adhesive layers
Solution Approach 1:
The patent changes the physical parameters of the adhesive layers by making them have different thicknesses. Specifically, the adhesive layer between the wiring board and the lowermost semiconductor chip is made thicker than the adhesive layer between the uppermost semiconductor chip and the chip stack. This parameter change compensates for the thermal expansion differences and reduces warpage during the sealing process.
Solution Approach 2:
The patent applies local quality by creating non-uniform adhesive layer thickness distribution in different locations of the chip stack structure. The adhesive layers are designed with varying thicknesses at different positions to locally compensate for thermal expansion coefficient differences between the sealing insulation layer and the adhesive layers, thereby preventing warpage and deformation.
2Strength
If adhesive layers are used to bond semiconductor chips to the wiring board, then the chips are securely mounted, but displacement and deformation occur during sealing due to thermal expansion differences
Solution Approach 1:
The patent changes the thickness parameter of the adhesive layers to optimize both bonding strength and position precision. By making the adhesive layer between the wiring board and the lowermost chip thicker than other adhesive layers, it provides sufficient bonding strength while compensating for thermal expansion differences, thereby maintaining chip position precision during sealing.
Solution Approach 2:
The patent applies beforehand cushioning by designing thicker adhesive layers in advance to compensate for the expected thermal expansion differences during the sealing process. This pre-compensation prevents displacement and deformation before they occur, ensuring manufacturing precision is maintained.
3Ease of manufacture
If uniform thickness adhesive layers are used between semiconductor chips, then manufacturing is simplified, but bonding wires may contact semiconductor chips causing defects
Solution Approach 1:
The patent applies local quality by creating non-uniform adhesive layer thicknesses at specific locations. The adhesive layer between the wiring board and the lowermost semiconductor chip is made thicker to prevent bonding wires from contacting the chip, while other adhesive layers have different thicknesses. This localized variation ensures reliability without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes warpage and ensures high reliability by stabilizing the chip stack and preventing deformation during the sealing process, while also enhancing adhesiveness and reducing the risk of defects like voids and tilting.
Implementation Method 1
differences in thermal expansion coefficients between the sealing insulation layer and adhesive layers
Data Source
AI summary
A semiconductor device includes: a wiring board, a chip stack provided above the wiring board and including a first semiconductor chip; a second semiconductor chip provided between the wiring board and the first semiconductor chip; a first adhesive layer provided between the first semiconductor chip and the second semiconductor chip and on the second semiconductor chip; and a sealing insulation layer including a first part and a second part, the first part covering the chip stack, and the second part extending between the wiring board and the first semiconductor chip.