Chip-Stacked Image Sensor Maximizing Photodiode Area
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Solution Overview
Problem
Conventional image sensors face a reduction in photodiode area and available charge due to the large areas occupied by metal lines for signal transmission, which affects image quality and dynamic range, especially as pixel size decreases.
Innovation Solution
A chip-stacked image sensor design where image signal sensing cells with photodiodes and charge transmission transistors are embodied in one semiconductor chip, and image signal conversion cells with reset, conversion, and selection transistors are in another, maximizing photodiode area and allowing separate output of image charges to reduce signal processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional image sensor cells with multiple transistors are used, then signal transmission and control functions are achieved, but metal line areas increase reducing photodiode area
Solution Approach 1:
The image sensor is divided into two separate chips: a first chip containing only photodiodes and charge transmission transistors, and a second chip containing reset, conversion, and selection transistors. This segmentation eliminates the need for extensive metal lines on the first chip, maximizing photodiode area while maintaining all necessary signal transmission and control functions through the chip stack interface.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By moving transistor functions to a second chip layer, the design utilizes the vertical dimension to resolve the conflict between photodiode area and metal line area, allowing both functions to coexist without spatial interference.
2Quantity of substance
If pixel size is reduced, then sensor resolution increases, but photodiode area and available charge decrease
Solution Approach 1:
By separating charge transmission functions from other transistor functions into distinct chips, the patent minimizes the area consumed by metal lines and transistors on the photodiode chip. This allows photodiodes to occupy a larger proportion of each pixel area, maintaining available charge even as overall pixel size decreases for higher resolution.
3Device complexity
If multiple transistors are combined in one cell, then transistor count reduces, but metal line area increases occupying photodiode space
Solution Approach 1:
The patent segments transistor functions across two chips: charge transmission transistors remain on the first chip with photodiodes, while reset, conversion, and selection transistors are moved to the second chip. This eliminates the need for extensive metal line interconnections that would otherwise occupy photodiode area, while maintaining reduced overall transistor complexity through shared resources.
Solution Approach 2:
The chip stack interface acts as an intermediary, enabling charge transmission from the first chip to the second chip where additional transistor functions are performed. This mediator approach allows functional integration without requiring all transistors to coexist in the same planar space with photodiodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design maximizes the photodiode area, increasing the amount of available charge and improving image quality by allowing rapid and accurate processing of image charges without the need for distinguishing signals from multiple filters, thus enhancing the dynamic range and reducing signal processing time.
Implementation Method 1
at least four photodiodes PD(0,0), PD(1,1), PD(1,0) and PD(2,1) for sensing image signals and generating image charges
Data Source
AI summary
A chip-stacked image sensor obtained by embodying an image sensor cell in two chips and combining the chips with each other is provided. The chip-stacked image sensor includes first and second semiconductor chips. The first semiconductor chip includes a plurality of image signal sensing cells for generating image charges corresponding to image signals sensed by at least four photodiodes and outputting the generated image charges through at least two common terminals and a plurality of image charge transmission pads. The second semiconductor chip includes a plurality of image signal conversion cells for converting the image signals into electrical signals and a plurality of image charge receiving pads. Here, the image charges generated by the image signal sensing cells are transmitted to corresponding image signal conversion cells via the plurality of image charge transmission pads and the plurality of image charge receiving pads.