Chip-Stacked Semiconductor Isolation Trench Segmentation
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Solution Overview
Problem
Conventional methods for forming isolation trenches in chip-stacked semiconductor devices are inefficient due to long etching times and high costs, leading to incomplete filling of trenches with thermal oxide films, which complicates the process and increases chip area.
Innovation Solution
A method involving the direct formation of a silicon film on the inner and outer surfaces of the isolation trench, followed by an insulation film to fill gaps, and grinding the rear surface to expose the trench, allowing for a through electrode to be formed without increasing the chip area and maintaining etching rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the isolation trench is formed to be narrow to reduce dead space, then the chip area is reduced, but the etching time increases significantly and cost increases
Solution Approach 1:
The patent segments the isolation trench formation process into two distinct stages: first forming a wide preliminary trench using a first etching method, then forming the final narrow isolation trench using a second etching method. This segmentation allows each etching step to operate at optimal conditions - the first etching handles bulk material removal efficiently, while the second etching achieves precise narrow dimensions, thereby resolving the contradiction between narrow trench width and etching time
Solution Approach 2:
The patent performs preliminary action by forming a preliminary isolation trench with wider width before forming the final narrow isolation trench. This preliminary wide trench serves as a precursor structure that facilitates subsequent precise etching, allowing the final narrow trench to be formed more efficiently than attempting to etch the narrow trench directly from the substrate
2Area of stationary object
If the isolation trench is formed to be narrow to reduce dead space, then the chip area is reduced, but the manufacturing cost increases
Solution Approach 1:
The patent segments the etching process into two stages with different methodologies, allowing optimization of each stage for its specific purpose. The first etching stage uses parameters optimized for high-speed bulk removal, while the second stage uses parameters optimized for precision narrow trench formation, thereby reducing overall manufacturing cost compared to using a single slow precision etching process for the entire trench
3Manufacturing precision
If thermal oxide film is used to fill the isolation trench, then the trench cannot be completely filled, so polycrystalline silicon film must be embedded, which complicates the process
Solution Approach 1:
The patent changes the material parameter from thermal oxide film to silicon film for filling the isolation trench. This parameter change is critical because silicon film has different physical properties - specifically it can be etched selectively and provides complete filling capability, thereby eliminating the need for the two-film approach (thermal oxide + polycrystalline silicon) and simplifying the overall process
4Productivity
If the isolation trench width is increased to improve etching rate, then the etching time is reduced, but the dead space increases and chip area increases
Solution Approach 1:
The patent segments the trench width into two stages: a wide preliminary trench that enables high etching rate, and a narrow final isolation trench that minimizes dead space. The first etching forms the wide trench quickly to improve productivity, then the second etching refines it to the narrow final dimensions, thereby achieving both high etching rate and minimal chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the dead space in the isolation trench, decreases the chip area, and enhances the etching rate by treating the silicon film within the trench as part of the substrate, improving the efficiency of the chip-stacked semiconductor device manufacturing process.
Implementation Method 1
By thermally oxidizing the inner surface of the isolation trench 11, a silicon thermal oxide film 12 that covers the inner surface of the isolation trench 11 is formed
Implementation Method 2
a rear surface grinding step of grinding a rear surface of the silicon substrate 100 to expose the isolation trench 103 to the rear surface side of the silicon substrate 100
Data Source
AI summary
A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films.