Chip-Stacked Semiconductor Package Warpage Control
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Solution Overview
Problem
Current semiconductor package technologies face challenges in creating miniaturized, multifunctional, and high-capacity chip-stacked semiconductor devices that efficiently connect multiple chips while maintaining structural integrity and preventing warpage.
Innovation Solution
The proposed solution involves a chip-stacked semiconductor package design with a first chip and a second chip, where the first chip includes real bump pads and dummy bump pads connected through real and bridge dummy bumps, and a sealing member such as an underfill and molding member to secure the chips, with specific configurations of through silicon vias and connection members to enhance electrical and physical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked to increase capacity and miniaturization, then device functionality and integration density are improved, but structural integrity and warpage control deteriorate
Solution Approach 1:
The chip stack is divided into multiple discrete chip layers (first chip, second chip, third chip) connected through intermediate connection structures. Each chip can be independently manufactured and tested before stacking, allowing for better control of individual chip properties while achieving high integration density through vertical arrangement.
Solution Approach 2:
Different regions of the chip stack are assigned different functions: real bump pads and real bumps for electrical connection, dummy bump pads and bridge dummy bumps for mechanical support and warpage compensation. The sealing member is applied selectively to protect specific areas. This local differentiation allows optimization of each region for its specific purpose while maintaining overall structural integrity.
2Reliability
If real bump pads and real bumps are used for electrical connection, then electrical connectivity is improved, but mechanical stability and warpage resistance worsen
Solution Approach 1:
The patent merges electrical connection function and mechanical support function into a unified chip stack structure. Real bumps provide both electrical connectivity and partial mechanical support, while bridge dummy bumps connect dummy bump pads to provide additional mechanical stability and distribute thermal stress, preventing warpage without interfering with the electrical connection path.
Solution Approach 2:
Bridge dummy bumps act as intermediary structures between real bumps and dummy bump pads. These intermediary elements help distribute mechanical stress and compensate for thermal expansion differences between layers, reducing warpage while allowing real bumps to maintain their primary electrical connection function.
3Volume of moving object
If chip size is reduced for miniaturization, then device compactness is improved, but manufacturing precision and connection reliability worsen
Solution Approach 1:
The patent transitions from horizontal expansion to vertical stacking, arranging multiple chips in the vertical dimension (z-axis) rather than expanding the planar footprint. This dimensional change achieves miniaturization by utilizing the third dimension, allowing smaller individual chips to be connected through vertical bump structures with controlled precision.
Solution Approach 2:
Bump pads and bumps are pre-formed on each chip before stacking, with precise positioning and dimensional control achieved during individual chip fabrication. This preliminary formation of connection structures ensures high manufacturing precision is maintained even as chip size is reduced, because the critical connection features are defined early in the manufacturing process with appropriate tolerances.
4Stability of the object's composition
If dummy bump pads and bridge dummy bumps are added for structural support, then warpage mitigation is improved, but device complexity increases
Solution Approach 1:
Dummy bump pads and bridge dummy bumps serve multiple functions simultaneously: they provide mechanical support to prevent warpage, distribute thermal stress across the chip stack, and maintain alignment between layers during assembly. By designing these structures to fulfill multiple roles, the patent reduces overall device complexity compared to having separate dedicated components for each function.
Data Source
AI summary
A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.