Chip Stacked Structure with Thicker Top Semiconductor for Bending Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to reduce the thickness of semiconductor devices while minimizing thermal stress-induced concave-bending, which can lead to cracks in semiconductor chips, particularly in chip-on-chip technology where stacked chips face increased thickness and thermal expansion mismatch issues.
Innovation Solution
The solution involves a chip stacked structure where a thicker semiconductor chip is positioned at the top, with its circuit formation surface facing the thinner chips, and a sealing process using a first and second sealing member to manage thermal stress, ensuring the thicker chip absorbs the contraction force and reduces bending, while maintaining high-density packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of individual semiconductor chip is reduced to reduce total thickness, then the total thickness of the semiconductor device is reduced, but thermal stress increases causing concave-bending and cracks
Solution Approach 1:
The patent applies local quality by making the top semiconductor chip thicker than the other chips in the stack. Specifically, the top chip has a thickness of 1.5 times or more compared to other chips, creating a localized thickness variation that provides mechanical reinforcement exactly where thermal stress is most intense, thereby preventing concave-bending and cracks while maintaining overall device thinness
Solution Approach 2:
The patent implements beforehand cushioning by pre-positioning a thicker semiconductor chip at the top of the stack before thermal processing occurs. This thicker chip acts as a preventive measure that absorbs and distributes thermal stress before it can cause damage to thinner chips, cushioning against the harmful effects of thermal expansion mismatch during subsequent manufacturing processes
2Quantity of substance
If multiple semiconductor chips are stacked to achieve high density packaging, then packaging density is improved, but device thickness increases
Solution Approach 1:
The patent applies parameter changes by varying the thickness parameter of semiconductor chips within the stack. Instead of using uniform thickness, the top chip is made significantly thicker (1.5 times or more) while other chips maintain thinner profiles, allowing the device to accommodate multiple chips vertically while controlling overall thickness through strategic parameter variation
Solution Approach 2:
The patent utilizes another dimension by transitioning from two-dimensional lateral expansion to three-dimensional vertical stacking with variable thickness. By stacking chips vertically and varying thickness in the vertical dimension, the design achieves high packaging density without proportionally increasing device thickness, as the thicker top chip compensates for stress rather than adding functional layers
3Ease of manufacture
If uniform thickness chips are used in stack, then manufacturing is simplified, but thermal stress distribution is uneven causing top chip bending
Solution Approach 1:
The patent resolves this contradiction by applying local quality - while most chips in the stack maintain uniform thickness for ease of manufacture, the top chip is specifically made thicker (1.5 times or more) to provide localized mechanical reinforcement. This selective thickness variation maintains manufacturing simplicity for the majority of chips while stabilizing the shape of the top chip against thermal stress-induced bending
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses concave-bending and prevents cracks in semiconductor chips, allowing for thinner, high-density semiconductor devices with improved bending resistance and manufacturing yield.
Implementation Method 1
thermal stress due to difference in thermal expansion between sealing resin and the semiconductor chip
Implementation Method 2
the thicker chip absorbs the contraction force and reduces bending
Data Source
AI summary
A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.