Chip-Stacked Semiconductor Package TSV Manufacturing
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing small-sized, multifunctional, and high-capacity semiconductor products with high reliability at a low cost, particularly in effectively stacking and packaging multiple chips while ensuring electrical connectivity and mechanical stability.
Innovation Solution
A method for manufacturing a chip-stacked semiconductor package involves preparing a base wafer with through-silicon vias (TSVs), bonding it to a supporting carrier, stacking additional chips on the base wafer, sealing the chips with a sealing portion, and separating them, using techniques such as underfilling and sawing to ensure electrical connectivity and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are stacked to increase capacity and functionality, then the semiconductor package achieves high functionality and high capacity, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: preparing base wafers with TSVs, bonding second chips to first chips, sealing the stacked chips, and separating the finished packages. This segmentation allows each stage to be optimized independently, managing the overall manufacturing complexity while achieving multi-chip stacking functionality.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional stacking by bonding multiple chip layers vertically. This dimensional change enables high functionality and capacity within a compact footprint, as multiple chips are arranged in the vertical dimension rather than requiring extensive horizontal space.
2Volume of moving object
If chips are stacked closely to reduce package size, then compactness is achieved, but maintaining electrical connectivity and mechanical stability becomes more difficult
Solution Approach 1:
The patent implements a nested structure where second chips are bonded onto first chips, which themselves are mounted on a supporting carrier. This nested arrangement allows compact vertical stacking while maintaining proper electrical connections through TSVs and bonding interfaces, achieving space efficiency without sacrificing reliability.
Solution Approach 2:
The supporting carrier acts as an intermediary substrate that facilitates the bonding of first chips with TSVs, which in turn support second chips. This intermediary structure provides mechanical stability and electrical connectivity pathways, enabling reliable compact stacking by mediating the connections between multiple chip layers.
3Manufacturing precision
If advanced bonding and sealing techniques are used to ensure reliability, then manufacturing precision improves, but the ease of manufacture decreases
Solution Approach 1:
The patent performs preliminary actions by pre-forming TSVs in the first chips before bonding, and by preparing the supporting carrier in advance. These preliminary steps establish the electrical and mechanical foundation early in the process, enabling subsequent bonding and sealing operations to proceed with higher precision while managing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of compact, high-capacity semiconductor packages with improved reliability and functionality by effectively stacking multiple chips while maintaining electrical connections and mechanical integrity, facilitating efficient manufacturing and testing processes.
Implementation Method 1
forming the TSV extending in the semiconductor substrate through the interlayer insulation layer
Implementation Method 2
bonding the base wafer including the plurality of first chips to a supporting carrier
Implementation Method 3
filling a connection portion between the first chips and the second chips with an underfill
Implementation Method 4
separating the stacked chips from each other
Data Source
AI summary
A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.