Chip-Stacked Semiconductor Package With Symmetric TSV Connections
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Solution Overview
Problem
The semiconductor industry faces challenges in creating compact, multi-functional, high-capacity semiconductor packages with high reliability at low costs, particularly in efficiently stacking and sealing chips to optimize performance and reduce manufacturing costs.
Innovation Solution
A chip-stacked semiconductor package design involving a first and second chip with through-silicon vias (TSVs) and symmetric connection members, sealed with underfills and molding members, where the second chip is stacked directly on the first chip without a temporary carrier wafer, allowing for reduced manufacturing costs and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are stacked using conventional methods with temporary carrier wafers, then alignment and positioning are easier, but manufacturing costs increase and device size increases
Solution Approach 1:
The patent removes the temporary carrier wafer from the chip stacking process entirely. Chips are directly stacked and bonded to each other without requiring a carrier substrate, which eliminates the additional manufacturing steps of mounting chips to the carrier, aligning multiple layers relative to the carrier, and subsequently removing the carrier. This extraction of the unnecessary carrier component directly reduces manufacturing cost while the direct chip-to-chip bonding simplifies the overall process complexity.
Solution Approach 2:
The patent merges the alignment and bonding operations into a single integrated process. By eliminating the carrier wafer intermediary, the method combines chip placement, alignment, and bonding into a direct chip-to-chip stacking operation. This merging reduces the number of discrete manufacturing steps, lowers process complexity, and eliminates the costs associated with carrier wafer fabrication and handling.
2Reliability
If conventional sealing methods are used with molding compound, then chip connections are protected, but heat dissipation efficiency decreases
Solution Approach 1:
The patent applies selective sealing where only the necessary connection regions between stacked chips are sealed using underfill material, rather than encapsulating the entire chip stack with molding compound. This local quality approach provides adequate protection for the critical bond interfaces while leaving the majority of chip surfaces exposed, thereby maintaining efficient heat dissipation pathways from the active chip regions to the external environment.
Solution Approach 2:
The patent uses thin underfill films applied at the chip interfaces rather than thick molding compound encapsulation. These thin film seals provide sufficient mechanical protection and environmental sealing for the connection regions while minimizing thermal resistance. The thin film structure allows heat to conduct more efficiently through and around the sealed regions compared to bulky molding compound.
3Manufacturing precision
If symmetric connection members are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs asymmetric connection member configurations where the shape, size, or distribution of connection members on one chip surface differs from the other. This asymmetry is strategically designed to achieve self-alignment during stacking, where the unique geometric features guide precise positioning without requiring complex symmetric patterns. The asymmetric design simplifies the manufacturing process by reducing the precision requirements for pattern replication while maintaining accurate alignment.
Data Source
AI summary
A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.