Chip Stacking on Base Wafer Using Carrier Support
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Solution Overview
Problem
Current methods for producing 3D Integrated Chips (3D ICs) face challenges such as low throughput, high production costs, and poor silicon utilization due to difficulties in handling wafers and managing thermal expansion during the chip-to-wafer (C2W) process, leading to inefficient chip stacking and bonding.
Innovation Solution
The method involves fixing the base wafer to a carrier during chip stacking and heat treatment, allowing for simultaneous processing of multiple wafers and reducing thermal stress by isolating the base wafer into sections, enabling precise positioning and bonding of chips with improved throughput and handling, and using a carrier made of silicon or glass to manage thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the base wafer is made thinner and/or larger to increase chip stacking density, then chip packing density is improved, but handling difficulty increases and risk of breaking increases
Solution Approach 1:
A carrier wafer is introduced as an intermediary substrate to support the base wafer during the chip stacking process. The carrier wafer has higher mechanical strength and allows handling without directly manipulating the thin base wafer, thus preventing breakage while enabling high-density chip stacking on the base wafer.
Solution Approach 2:
The base wafer is divided into multiple isolated sections or islands, each capable of being processed independently. This segmentation reduces the overall handling area of the thin base wafer, making it easier to manage while maintaining high chip stacking density in each section.
2Reliability
If chips are stacked on a base wafer and then heat treated for bonding, then bonding quality is improved, but thermal expansion differences cause stress and deformation
Solution Approach 1:
The base wafer is divided into multiple isolated sections, each surrounded by separation structures. This segmentation isolates the thermal expansion of each section, preventing stress propagation across the entire wafer and reducing deformation during heat treatment while maintaining bonding quality.
Solution Approach 2:
Separation structures are pre-formed around each section of the base wafer before chip stacking and heat treatment. These structures preemptively counteract thermal expansion stress by providing physical isolation, preventing stress accumulation and deformation during subsequent bonding processes.
3Manufacturing precision
If chip stacking and heat treatment are performed as separate process steps, then process control is improved, but throughput is reduced
Solution Approach 1:
The chip stacking process and heat treatment process are merged into a single integrated process step. Chips are stacked on the base wafer and immediately heat treated in the same processing cycle, eliminating the need for separate handling and transport steps while maintaining process control through the carrier wafer support system.
4Ease of operation
If a carrier is used to support the base wafer, then handling is improved, but device complexity increases
Solution Approach 1:
The carrier wafer is made from the same material as the base wafer (silicon), creating homogeneity in material properties. This simplifies the overall system by eliminating material incompatibilities and allowing the carrier to be processed using the same techniques as the base wafer, reducing process complexity while maintaining handling ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances throughput, reduces production costs, and improves chip yield by allowing for precise chip placement and bonding, accommodating chips of different sizes, and minimizing thermal stress, resulting in higher-quality 3D ICs with better handling and integration capabilities.
Implementation Method 1
different thermal expansions of the various materials of the various components present in the chip stacks are problematic during production
Implementation Method 2
fixing the base wafer on a carrier or connecting it to a carrier
Data Source
Figure 1
Figure 2a~2f
Figure 2g~2n
AI summary
A method for bonding a plurality of chips (3) onto a base wafer (1) containing chips (3') on its front side, wherein the chips (3) are stacked in at least one layer on the back side of the base wafer (1) and electrically conductive connections (7) are made between the vertically adjacent chips (3, 3'), comprising the following steps: a) fixing a front side (2) of the base wafer (1) onto a support (5), b) placing at least one layer of chips (3) in defined positions on a back side (6) of the base wafer (1), and c) heat-treating the chips (3, 3') on the base wafer (1) fixed to the support (5), characterized in that, prior to step c), the chips (3') of the base wafer (1) are at least partially separated into separate chip stack sections (1c) of the base wafer (1).