Redistribution-Layer Chip Stacking for Compact Semiconductor Packages
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Solution Overview
Problem
The challenge in semiconductor packaging is to achieve miniaturization and weight reduction while maintaining high performance, particularly in portable devices, where existing technologies face difficulties in efficiently integrating semiconductor devices with short interface paths and reducing package size.
Innovation Solution
A semiconductor package design that includes a redistribution structure with multiple semiconductor chips stacked vertically, using through-electrodes and conductive posts to connect the chips, and a molded portion to surround the chips, allowing for a second redistribution structure to connect the upper pads and conductive posts, thereby shortening interface paths and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are vertically stacked with multiple conductive posts for connection, then electrical connectivity between chips is improved, but package size and complexity increase
Solution Approach 1:
The patent merges the functions of multiple conductive posts into a single integrated redistribution structure that provides both mechanical support and electrical connectivity between stacked chips, eliminating the need for separate conductive posts and reducing package volume
Solution Approach 2:
The redistribution structure serves multiple functions simultaneously: it acts as an interconnection layer for electrical signals, provides mechanical support for the stacked chips, and enables both chip-to-chip and chip-to-package external connections, replacing what would traditionally require multiple separate components
2Reliability
If more conductive posts are used to connect chips vertically, then signal transmission reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the electrical interconnection function and mechanical support function into a single redistribution structure, reducing the total number of components and simplifying the manufacturing process while maintaining reliable signal transmission between stacked chips
3Speed
If interface paths between chips are made shorter for improved performance, then signal transmission speed is improved, but package design complexity increases
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking, fundamentally changing the spatial dimension of interchip communication. This vertical integration dramatically shortens signal transmission paths while the redistribution structure provides a systematic methodology for managing the increased design complexity
Data Source
AI summary
A semiconductor package includes a first redistribution structure having a first redistribution layer; a first semiconductor chip on the first redistribution structure, and having first lower pads, first upper pads, and first through-electrodes; a second semiconductor chip on the first semiconductor chip, and having second lower pads, second upper pads, and second through-electrodes; a vertical connection conductor on the first redistribution structure, and connected to the first redistribution layer; a molded portion on the first redistribution structure, and surrounding the first second semiconductor chips; a second redistribution structure on the second semiconductor chip and the vertical connection conductor, the second redistribution structure having a second redistribution layer connected to the second upper pads and the vertical connection conductor; and a third semiconductor chip on the second redistribution structure, and having contact pads connected to the second redistribution layer.