Chip Stacking Structure With Heterogeneous Redistribution Layers
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Solution Overview
Problem
The challenge of reducing the plane dimension of chips in electronic devices is hindered by the large size of single chips, even when using three-dimensional stacking, due to redundant interface circuits in homogeneous redistribution layer designs.
Innovation Solution
Implementing a heterogeneous design for redistribution layers on stacked chips, where each layer is insulated and patterned differently to reduce redundancy, allowing independent signal transmission through separate interface circuits, and using through silicon vias to connect these layers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If homogeneous redistribution layer design is used with multiple interface circuits, then all chips can be universally connected, but the plane dimension of the chip increases due to redundant interface circuits
Solution Approach 1:
The patent applies local quality by making each redistribution layer heterogeneous with unique patterns and characteristics. Each layer has specifically designed metal traces and interface circuits tailored to its particular function and position in the stack, rather than using identical homogeneous designs across all layers. This allows each chip to have optimized local interface configurations that reduce redundancy while maintaining necessary connectivity.
Solution Approach 2:
The patent segments the interface circuit functionality across different redistribution layers. Instead of having all interface circuits on every chip, the interface functions are divided and distributed among specific layers. Each redistribution layer has its own dedicated interface circuits that connect to specific external components, eliminating the need for redundant interface circuits on all chips.
2Reliability
If multiple interface circuits are disposed on each chip for vertical interconnection, then signal transmission between stacked chips is enabled, but the chip area increases
Solution Approach 1:
The patent extracts the interface circuit functionality from every chip and concentrates it on specific redistribution layers. By taking out the redundant interface circuits from chips that don't need them and leaving only the necessary interface circuits on chips with active redistribution layers, the chip area is reduced while maintaining signal transmission capability through the stacked structure.
Solution Approach 2:
The patent moves interface circuit functionality from a two-dimensional plane on each chip to a three-dimensional distributed architecture across multiple stacked layers. Interface circuits are positioned in the vertical dimension on specific redistribution layers rather than being uniformly distributed across all chips in the plane, reducing the area required on individual chips while maintaining overall connectivity.
3Area of moving object
If heterogeneous redistribution layers with different patterns are used, then redundancy is reduced and chip area is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-planning and pre-designing the heterogeneous redistribution layer patterns during the chip fabrication process. The different metal trace patterns and interface circuit configurations are incorporated into the chip design before stacking, allowing for systematic manufacturing rather than post-assembly customization. This reduces manufacturing complexity compared to trying to assemble pre-made homogeneous chips into heterogeneous configurations.
Data Source
AI summary
In a chip stacking structure, a third die, a second die, and a first die are sequentially stacked on a carrier board. A first redistribution layer and a first interface component of the first die form a first interface circuit, and a second redistribution layer and a second interface component of the second die form a second interface circuit. A first conductive structure penetrates through at least the second die and the third die, and a second conductive structure penetrates through at least the third die. The first interface circuit of the first die and the second interface circuit of the second die are separately electrically connected to another component through the insulated first conductive structure and the insulated second conductive structure.