Chip Stacking Structure With Multi-Layer Interconnects for Higher Bandwidth
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Solution Overview
Problem
Existing chip stacking structures face limitations in bandwidth support as data communication demands increase, necessitating improved signal transmission paths.
Innovation Solution
The introduction of a chip stacking structure with multiple redistribution layers and conductive channels, including a first and second conductive channel, to enhance signal interconnection and interworking between chips, allowing for increased bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional μBump and TSV structure is used for chip interconnection, then the structure is simple, but the bandwidth supported is insufficient for high-speed data communication
Solution Approach 1:
The patent transitions from a single-conductive-path architecture to a multi-dimensional conductive channel system. Multiple conductive channels (first conductive channel, second conductive channel, third conductive channel) are introduced to create parallel signal transmission paths, effectively increasing bandwidth capacity while maintaining structural organization through systematic layering and spatial arrangement.
Solution Approach 2:
The interconnection structure is segmented into multiple independent conductive channels distributed across different chips and redistribution layers. Each channel operates as a separate transmission path, allowing parallel data communication and increasing overall bandwidth. The segmentation is implemented through distinct conductive channels connecting different functional blocks across chip boundaries.
2Reliability
If multiple conductive channels and redistribution layers are added to increase bandwidth, then the data communication capacity is improved, but the device complexity increases
Solution Approach 1:
The redistribution layers serve multiple functions simultaneously: they redistribute electrical signals to appropriate destinations, provide mechanical support for conductive channels, enable both intra-chip and inter-chip connections, and facilitate signal routing across different packaging configurations. This multi-functionality reduces the need for separate dedicated structures for each function.
Solution Approach 2:
The patent merges the functions of signal redistribution, mechanical support, and electrical interconnection into integrated structures. Redistribution layers are combined with conductive channels and chip substrates to create unified interconnection systems that achieve multiple objectives simultaneously, thereby managing complexity through functional integration rather than separate components.
3Ease of manufacture
If chips are aligned and tested individually in traditional processes, then the preparation process is straightforward, but the production efficiency is low and costs are high
Solution Approach 1:
Conductive channels are formed within chips before the chips are packaged and stacked. Redistribution layers are prepared on chip surfaces in advance of final assembly. This preliminary preparation of conductive pathways and connection structures enables more efficient subsequent assembly processes and reduces the need for complex post-assembly alignment and testing operations.
Solution Approach 2:
The conductive channels and redistribution layers are designed to automatically align and connect chips during the stacking process without requiring extensive external alignment equipment or manual intervention. The structures self-align through their geometric configurations and bonding mechanisms, reducing manufacturing complexity and improving production efficiency through automated self-assembly characteristics.
Data Source
AI summary
A chip stacking structure includes: a first chip, a second chip stacked with the first chip, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first conductive channel, and a second conductive channel; the first redistribution layer is disposed on a surface of the first chip facing the second chip; the second redistribution layer is disposed on a passive surface of the second chip, and the third redistribution layer is disposed on an active surface of the second chip; the first conductive channel passes through the second chip and the third redistribution layer, connecting the first redistribution layer and the second redistribution layer; and the second conductive channel passes through the second chip, connecting the second redistribution layer and the third redistribution layer.