3D Chip Stacking With Impedance Elements For Compact Wireless Devices
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Solution Overview
Problem
Current 3D IC integration technologies face challenges in reducing circuit size while maintaining performance, particularly in handheld wireless devices, where passive electronic elements occupy significant space without compromising electrical properties.
Innovation Solution
A chip stacking structure utilizing microbump structures and redistribution layers to form impedance elements, such as inductance and capacitance elements, which are electrically connected to provide specific oscillation frequencies, enhancing structural strength and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional package technology is used, then device size is larger, but circuit performance and computing capability are reduced
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple chips are stacked in the vertical dimension and interconnected through TSVs, enabling higher computing capability within a smaller footprint while maintaining signal integrity through controlled impedance pathways.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked vertically with interposer layers embedded between them. The interposer contains TSVs that penetrate through substrate layers, creating a nested configuration where connection pathways are embedded within the stacked chip structure rather than extending externally.
2Reliability
If TSV interposer structure is used, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection structure into segmented functional layers: chip layers, interposer layers, and space layers. Each layer is manufactured and prepared separately with specific functions (signal transmission, mechanical support, alignment), then assembled together. This segmentation simplifies the manufacturing process by allowing parallel processing of individual layers before final stacking.
Solution Approach 2:
The patent introduces interposer layers as intermediary structures between stacked chips. These interposer layers contain TSVs that mediate the electrical connection between chips, providing controlled impedance pathways and signal routing functionality. The interposer acts as a buffer that simplifies direct chip-to-chip interfacing by providing a standardized connection interface.
3Area of stationary object
If chips are stacked closely to reduce size, then device footprint is reduced, but signal loss increases
Solution Approach 1:
The patent controls signal integrity by managing impedance parameters throughout the stacked structure. Redistribution layers are designed with specific trace patterns and geometries to maintain controlled impedance (e.g., 50 ohm differential pairs). The space layers are engineered with specific dielectric properties and thicknesses to minimize signal attenuation while maintaining compact dimensions.
Solution Approach 2:
The patent moves signal pathways from external planar routes to vertical three-dimensional pathways through TSVs. This vertical routing through the stacked structure reduces the physical distance signals must travel laterally, minimizing signal loss while achieving compact footprint. The TSVs provide direct vertical conduits that shorten inter-chip signal paths compared to traditional edge-board routing.
Data Source
AI summary
A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.