Heterogeneous Chip Stacking With Direct Convex Pillar Bonding

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Solution Overview

Problem

The existing methods for heterogeneous chip stacking are inefficient in utilizing circuit substrate layout space, as they rely on pre-prepared solder balls that cannot effectively connect chips with small pad sizes or spacings, leading to inadequate electrical connections.

Innovation Solution

A method where two heterogeneous chips are stacked by directly contacting and tightly coupling convex pillar structures with bonding pad portions, using a combination of pressure, temperature, and ultrasonic frequency without pre-prepared solder balls, allowing for efficient electrical connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-prepared solder balls are used for chip stacking, then the electrical connection between chips and circuit substrate is established, but the layout space utilization is poor and small pad sizes cannot be effectively connected

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidcircuit substrate layout space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The invention changes the connection structure from spherical solder balls to columnar convex pillars with bonding pads. This parameter change allows the connection structure to be more space-efficient and enables reliable electrical connection for small pad sizes and spacings that cannot accommodate traditional solder balls.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The connection structure is segmented into distinct functional parts: the convex pillar body providing mechanical support and the bonding pad portions providing electrical connection. This segmentation allows optimization of each part's function, with the bonding pads being small and precise for high-density layouts.

Inventive Principle:

Principle #1Segmentation

2Reliability

If pre-prepared solder balls are placed in advance, then electrical connection is provided, but the manufacturing process becomes complex and space utilization is reduced

Engineering Contradiction:

Improveelectrical connectionVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention merges the formation of the convex pillar structure and the bonding pad into a single integrated structure formed directly on the chip. This eliminates the separate step of placing pre-prepared solder balls, simplifying the manufacturing process while maintaining reliable electrical connection.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The chip structure itself provides the connection elements (convex pillars with bonding pads) rather than requiring external placement of separate connection components. The chip is self-sufficient in providing both mechanical support and electrical connection functionality.

Inventive Principle:

Principle #25Self-service

3Area of stationary object

If solder ball size is reduced to accommodate small pad spacing, then connection between small pads is possible, but the solder ball reaches its minimum size limit and connection reliability deteriorates

Engineering Contradiction:

Improvepad spacingVSAvoidelectrical connection reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The invention changes the geometry from spherical solder balls to columnar convex pillars with flat bonding pad surfaces. This parameter change allows the connection structure to maintain adequate size for reliability while accommodating smaller pad spacings, as the columnar structure with flat bonding surfaces provides better mechanical and electrical contact than miniaturized spherical balls.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables effective stacking and electrical connection of chips with small pad sizes or spacings, enhancing the utilization of circuit substrate layout space and improving connection reliability.

Implementation Method 1

applying at least one of a predetermined pressure, a predetermined temperature, and a predetermined ultrasonic frequency to tightly couple the first bonding pad portions with the second bonding pad portions

Methodology Applied

Scientific EffectPressure: Pressure Increase

Implementation Method 2

Methodology Applied

Scientific EffectTemperature: Heating

Implementation Method 3

Methodology Applied

Scientific EffectUltrasonic frequency: Ultrasonic Vibration

Data Source

PatentUS20250105204A1Heterogeneous chip stacking method

Publication Date: 2025.03.27 SHINE OPTICS TECH CO LTD

AI summary

A heterogeneous chip stacking method includes providing a first chip, in which the first chip has a plurality of first convex pillar structures, and each first convex pillar structure has a first bonding pad portion; providing a second chip different from the first chip, in which the second chip has a plurality of second convex pillar structures, and each second convex pillar structures having a second bonding pad portion; placing the first chip on the second chip, in which the first bonding pad portions of the first convex pillar structures and the second bonding pad portions of the second convex pillar structures are in direct contact with each other respectively; and then applying at least one of a predetermined pressure, a predetermined temperature, and a predetermined ultrasonic frequency to tightly couple the first bonding pad portions and the second bonding pad portions with each other respectively.