3D Chip Stacking via Thermal Reflow Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density due to physical constraints in two-dimensional integrated circuits, including minimum component size and increased interconnections, which lead to circuit RC delay and power consumption issues, prompting the need for three-dimensional integrated circuits (3D ICs) to achieve higher device density.
Innovation Solution
The method involves a chip packaging process where chips are stacked with interconnects comprising a support structure and a bonding structure, using a thermal process to bond the chips, and a reflow process to secure the bonds, allowing for efficient stacking and bonding of multiple chips while minimizing thermal budget and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thermal bonding processes are used for stacking chips, then chips can be bonded together, but the thermal budget increases which causes low-k delamination
Solution Approach 1:
The patent changes the bonding parameters by using lower temperatures and shorter bonding times in the reflow process. Specifically, the reflow process is performed at temperatures below the melting point of the solder bump, typically in the range of 150-250°C, which is significantly lower than conventional high-temperature bonding processes. This parameter change reduces the thermal budget and prevents low-k delamination while still achieving reliable chip stacking through controlled solder reflow.
2Quantity of substance
If multiple chips are stacked using conventional processes, then device density increases, but the complexity of the stacking process increases
Solution Approach 1:
The patent applies preliminary action by pre-forming solder bumps on the chips before stacking. The solder bumps are created in advance with controlled height and diameter, and the chips are pre-aligned with registration marks. This preliminary preparation simplifies the actual stacking process, as the pre-formed solder bumps automatically provide mechanical alignment and the reflow process automatically bonds the chips together, reducing the complexity of real-time alignment and bonding operations.
3Strength
If chips are bonded with high thermal budget processes, then strong bonds are formed, but yield decreases due to low-k delamination
Solution Approach 1:
The patent utilizes phase transitions of the solder material to achieve strong bonds without high thermal budget. The reflow process heats the solder bump to its melting point, causing it to transition from solid to liquid phase, which enables the solder to flow and wet the chip surfaces, forming strong metallurgical bonds. The process then cools the solder back to solid phase, creating permanent strong bonds. This controlled phase transition occurs at relatively low temperatures, avoiding low-k delamination while ensuring strong bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher device density and reduced thermal budget, improving yield and reliability by allowing for re-workability during stacking and reducing the risk of low-k delamination, while maintaining a lower thermal budget compared to conventional processes.
Implementation Method 1
bonding the first chip and the second chip to each other via a thermal process applied to the bonding structure of the first interconnect
Implementation Method 2
reflowing the bond between the first chip and the second chip and simultaneously reflowing the bond between the second chip and the third chip
Data Source
AI summary
Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.