Semiconductor Chip Stacking With Resin Support for High-Aspect-Ratio Dies

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Solution Overview

Problem

Semiconductor chips with a high aspect ratio are difficult to appropriately dispose and stack in semiconductor packages due to their elongated shape, leading to potential inclination and instability during the packaging process.

Innovation Solution

The semiconductor device design includes a substrate with stacked semiconductor chips and resin layers, where at least one semiconductor chip extends over the controller chip, supported by bonding layers and a resin layer, allowing for effective displacement and stabilization of high-aspect-ratio chips during stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If semiconductor chips with high aspect ratio are mounted in the semiconductor package, then the device functionality is improved, but the chips cannot be appropriately disposed and stacked due to their elongated shape

Engineering Contradiction:
Improvedevice functionalityVSAvoidchip disposal and stacking
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar arrangement to three-dimensional stacked arrangement. Multiple semiconductor chips are disposed at different heights on the substrate, with lower-stage chips supporting upper-stage chips. This vertical stacking enables high-aspect-ratio chips to be properly positioned and stabilized, resolving the manufacturing difficulty while maintaining device functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If semiconductor chips with high aspect ratio are stacked, then the device integration is improved, but the chips may incline and become unstable during packaging

Engineering Contradiction:
Improvedevice integrationVSAvoidchip stability and alignment
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent employs underfill resin applied beforehand to the chips or substrate. This resin fills the gaps between chips and substrate, providing mechanical support and stabilization before the packaging process completes. The underfill prevents inclination and ensures stable positioning of high-aspect-ratio chips throughout packaging, maintaining both integration and stability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Device complexity

If multiple semiconductor chips are stacked to increase integration, then the device complexity is reduced, but the alignment precision of chips in higher stages deteriorates

Engineering Contradiction:
Improvedevice integrationVSAvoidchip alignment precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent introduces underfill resin as an intermediary material between chips and substrate. This resin provides a stable bonding interface that maintains precise alignment during the stacking and packaging processes. The underfill compensates for potential misalignments and ensures that chips in higher stages remain properly positioned, enabling increased integration without sacrificing alignment precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240421122A1Semiconductor device
Publication Date: 2024.12.19 KIOXIA CORP
  • US20240421122A1 patent drawing
  • US20240421122A1 patent drawing
  • US20240421122A1 patent drawing

AI summary

A semiconductor device according to an embodiment includes a substrate, a plurality of first semiconductor chips, a plurality of first resins, and a second semiconductor chip. The substrate has a first surface. The plurality of first semiconductor chips are stacked while being displaced in a direction substantially parallel to the first surface. The plurality of first resins are provided on respective lower surfaces of the plurality of first semiconductor chips. The second semiconductor chip is provided on the first surface. At least one of the plurality of first resins is in contact with an upper surface of the second semiconductor chip.