3D Chip Stacking With Shared Via and Redistribution Layers
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Solution Overview
Problem
The complexity and cost of manufacturing 3D chip stacking structures are increased due to the need for multiple via holes in conventional methods, which complicates the process and reduces production efficiency and increases costs.
Innovation Solution
A chip stacking structure with a redistribution layer system where each chip has a first redistribution layer connected to a corresponding chip, allowing electrical connection through a single via hole, simplifying the manufacturing process and reducing costs by eliminating the need for multiple via holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple via holes are formed to electrically connect chips to external circuits in conventional 3D chip stacking, then electrical connectivity is achieved, but manufacturing process complexity increases and production efficiency decreases
Solution Approach 1:
The patent segments the electrical connection function by introducing intermediate redistribution layers between chips and external circuits. Instead of forming multiple via holes through each chip to reach external circuits, the connection path is divided into segments: chip pads connect to first redistribution layer, which connects to second redistribution layer, which finally connects to external circuits. This segmentation reduces the number of via holes needed per chip while maintaining electrical connectivity.
Solution Approach 2:
The patent introduces redistribution layers as intermediary structures between chips and external circuits. These redistribution layers act as mediators that redistribute electrical connections, allowing multiple chips to share common via holes and connection paths. The intermediary layers enable electrical connectivity to be achieved with fewer via holes, thereby reducing manufacturing complexity.
2Reliability
If multiple via holes are formed for each chip in conventional methods, then electrical connection is established, but production costs increase
Solution Approach 1:
The patent makes via holes and redistribution layers universal by designing them to serve multiple chips simultaneously. A single via hole can provide electrical connection to multiple chips through the redistribution layer network. This multi-functionality reduces the total number of via holes needed across the entire chip stack, thereby lowering production costs while maintaining electrical connection reliability.
Solution Approach 2:
The patent merges the electrical connection functions of multiple chips by using shared redistribution layers and common via holes. Instead of dedicating separate via holes to each chip, the design combines connection paths so that via holes serve multiple chips. This merging approach reduces the total via hole count and associated manufacturing costs.
3Reliability
If via holes are formed multiple times to connect chips to external circuits, then electrical connectivity is achieved, but production efficiency is reduced
Solution Approach 1:
The patent performs preliminary action by forming redistribution layers and via holes at optimal stages during the stacking process. Instead of forming via holes multiple times after chip stacking, the design allows via holes to be formed once during wafer fabrication or at an early stacking stage, before final chip assembly. This preliminary formation of connection structures eliminates repeated via hole formation operations, thereby improving production efficiency.
Solution Approach 2:
The patent ensures continuity of useful action by designing the redistribution layer system to maintain electrical connectivity throughout the stacking process without requiring interruptive via hole formation operations. The continuous redistribution layer structure allows electrical connections to be established once and maintained through subsequent stacking operations, eliminating the need for repeated via hole formation and improving production efficiency.
Data Source
AI summary
A chip stacking structure includes a plurality of chips that are sequentially stacked and a first redistribution layer arranged on an active side of each chip. The plurality of chips include a first chip and a second chip that are located on an outermost side. Passive sides of the first chip and the second chip both face an outer side, and the chip stacking structure further includes a second redistribution layer arranged on the passive side of the first chip or the second chip. The second redistribution layer is electrically connected to at least one first redistribution layer through a first via hole.