Semiconductor Chip Stacking Using Stress Prediction to Reduce Warpage

The patent applies preliminary action by predicting stress characteristics of semiconductor chips before the stacking process. The system calculates stress characteristics based on wafer geometry data and chip position information in advance, allowing manufacturers to plan stacking combinations proactively. This prevents waste by identifying suitable chip pairs before actual stacking, rather than dealing with warpage issues after stacking has occurred.

The patent utilizes parameter changes by transforming physical wafer geometry parameters (shape, curvature) into predictive stress characteristic parameters. The system changes the state of information from raw geometric measurements to calculated stress predictions, enabling proactive stacking optimization. This parameter transformation allows the system to recommend stacking combinations that minimize warpage without requiring physical trial-and-error.

The patent replaces mechanical stress measurement systems with a computational prediction system. Instead of using complex mechanical apparatus to physically measure stress characteristics of each chip, the system substitutes this with algorithmic calculations based on wafer geometry data and chip position. This substitution maintains high manufacturing yield through accurate stress prediction while avoiding the complexity of direct mechanical measurement.

The patent introduces an intermediary computational model that bridges wafer geometry data and stress characteristics. Rather than directly measuring stress, the system uses wafer shape and curvature data as intermediaries to predict stress characteristics. This intermediary approach simplifies measurement by using easily obtainable geometric data to infer harder-to-measure stress parameters.

The patent performs preliminary data processing by calculating stress characteristics from wafer geometry data before chips are separated or stacked. This advance calculation allows the system to identify suitable stacking combinations and minimize chip waste before any physical processing occurs. The data processing complexity is concentrated in the preliminary stage, enabling waste reduction throughout the subsequent manufacturing process.

The patent applies segmentation by dividing the data processing into distinct components: wafer geometry data collection, local shape curvature calculation, and stress characteristic prediction. This segmentation of data processing tasks makes the overall complex process more manageable and systematic, allowing each component to be optimized independently while achieving the goal of minimizing chip waste through accurate stress prediction.